7-54
AT91CAP9A-DK Development Kit User Guide
6321B–CAP–02-Jul-07
VCCPD5
R12
3V3
VCCPD2
R21
3V3
VCCPD6
V12
3V3
VCCPD1
V21
3V3
VCCPD6
Y12
3V3
VCCPD1
Y21
3V3
B3
IO
ASDO
F17
ASDO
B3
CONF_DONE
CONF_DONE
J25
CONFIG_DONE
B3
IO
DATA0
H19
DATA0
B3
DCLK
DCLK
B31
DCLK
B5
CLK11n
INPUT
T4
EXT_CLK
B1
IO
CLK2p/DIFFIO_RX_C1p
U32
FPGA0
B1
IO
CLK2n/DIFFIO_RX_C1n
U31
FPGA1
B1
IO
DIFFIO_TX27p
U28
FPGA10
B2
IO
DIFFIO_RX50p
G28
FPGA100
B2
IO
DIFFIO_RX50n
G27
FPGA101
B2
IO
DIFFIO_TX50p
H28
FPGA102
B2
IO
DIFFIO_TX50n
H27
FPGA103
B2
IO
DIFFIO_RX49p
E30
FPGA104
B2
IO
DIFFIO_RX49n
E29
FPGA105
B2
IO
DIFFIO_TX49p
K27
FPGA106
B2
IO
DIFFIO_TX49n
K26
FPGA107
B2
IO
DIFFIO_RX48p
D32
FPGA108
B2
IO
DIFFIO_RX48n
D31
FPGA109
B1
IO
DIFFIO_TX27n
U27
FPGA11
B2
IO
DIFFIO_TX48p
J27
FPGA110
B2
IO
DIFFIO_TX48n
J26
FPGA111
B2
IO
DIFFIO_RX47p
F30
FPGA112
B2
IO
DIFFIO_RX47n
F29
FPGA113
B2
IO
DIFFIO_TX47p
L28
FPGA114
B2
IO
DIFFIO_TX47n
L27
FPGA115
B2
IO
DIFFIO_RX46p
G30
FPGA116
B2
IO
DIFFIO_RX46n
G29
FPGA117
B2
IO
DIFFIO_TX46p
L26
FPGA118
B2
IO
DIFFIO_TX46n
L25
FPGA119
B1
IO
DIFFIO_RX26p
AA32
FPGA12
Table 7-6. FPGA Pins Sorted by Signal Name (Continued)
Bank
Pin Type Name
Other Pin Information
Configuration
Function
Ball
Board Net
Содержание AT91CAP9
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