AT91CAP9A-DK Development Kit User Guide
7-61
6321B–CAP–02-Jul-07
B1
IO
DIFFIO_RX12p
AH32
FPGA68
B1
IO
DIFFIO_RX12n
AH31
FPGA69
B1
IO
DIFFIO_TX28n
U22
FPGA7
B1
IO
DIFFIO_TX12p
AA23
FPGA70
B1
IO
DIFFIO_TX12n
AA22
FPGA71
B1
IO
DIFFIO_RX11p
AE30
FPGA72
B1
IO
DIFFIO_RX11n
AE29
FPGA73
B1
IO
DIFFIO_TX11p
AB24
FPGA74
B1
IO
DIFFIO_TX11n
AB23
FPGA75
B1
IO
DIFFIO_RX10p
AJ32
FPGA76
B1
IO
DIFFIO_RX10n
AJ31
FPGA77
B1
IO
DIFFIO_TX10p
AC25
FPGA78
B1
IO
DIFFIO_TX10n
AC24
FPGA79
B1
IO
DIFFIO_RX27p
W32
FPGA8
B1
IO
DIFFIO_RX9p
AF30
FPGA80
B1
IO
DIFFIO_RX9n
AF29
FPGA81
B1
IO
DIFFIO_TX9p
AD25
FPGA82
B1
IO
DIFFIO_TX9n
AD24
FPGA83
B1
IO
DIFFIO_RX8p
AG30
FPGA84
B1
IO
DIFFIO_RX8n
AG29
FPGA85
B1
IO
DIFFIO_TX8p
AE26
FPGA86
B1
IO
DIFFIO_TX8n
AE25
FPGA87
B1
IO
DIFFIO_RX7p
AH30
FPGA88
B1
IO
DIFFIO_RX7n
AH29
FPGA89
B1
IO
DIFFIO_RX27n
W31
FPGA9
B1
IO
DIFFIO_TX7p
AE28
FPGA90
B1
IO
DIFFIO_TX7n
AE27
FPGA91
B1
IO
DIFFIO_RX6p
AF28
FPGA92
B1
IO
DIFFIO_RX6n
AF27
FPGA93
B1
FPLL8CLKn
INPUT
AJ29
FPGA94
B1
FPLL8CLKp
INPUT
AJ30
FPGA95
B2
FPLL7CLKp
INPUT
D30
FPGA96
B2
FPLL7CLKn
INPUT
D29
FPGA97
B2
IO
DIFFIO_TX51p
K25
FPGA98
B2
IO
DIFFIO_TX51n
K24
FPGA99
GND
A13
GND
Table 7-6. FPGA Pins Sorted by Signal Name (Continued)
Bank
Pin Type Name
Other Pin Information
Configuration
Function
Ball
Board Net
Содержание AT91CAP9
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