7-70
AT91CAP9A-DK Development Kit User Guide
6321B–CAP–02-Jul-07
B4
IO
DQ9T
D13
PISMO_FS1
B4
IO
DQSn9T
B13
PISMO_FS2
B4
IO
DQ9T
A14
PISMO_FS3
B4
IO
J15
PISMO_FS4
B4
IO
K16
PISMO_FS5
B4
IO
K17
PISMO_FS6
B4
IO
CLK12n
B16
PISMO_FS7
B4
IO
CLK12p
A16
PISMO_FS8
B4
IO
CLK13n
F16
PISMO_FS9
B6
IO
DIFFIO_RX111n
AF6
PISMO_NA0
B6
IO
DIFFIO_RX111p
AF5
PISMO_NA1
B6
IO
DIFFIO_TX108n
AC7
PISMO_NA10
B6
IO
DIFFIO_TX108p
AC6
PISMO_NA11
B6
IO
DIFFIO_RX108n
AJ2
PISMO_NA12
B6
IO
DIFFIO_RX108p
AJ1
PISMO_NA13
B6
IO
DIFFIO_TX107n
AC9
PISMO_NA14
B6
IO
DIFFIO_TX107p
AC8
PISMO_NA15
B6
IO
DIFFIO_RX107n
AE6
PISMO_NA16
B6
IO
DIFFIO_RX107p
AE5
PISMO_NA17
B6
IO
DIFFIO_TX106n
AB8
PISMO_NA18
B6
IO
DIFFIO_TX106p
AB7
PISMO_NA19
B6
IO
DIFFIO_TX110n
AD7
PISMO_NA2
B6
IO
DIFFIO_RX106n
AH2
PISMO_NA20
B6
IO
DIFFIO_RX106p
AH1
PISMO_NA21
B6
IO
DIFFIO_TX105n
AB10
PISMO_NA22
B6
IO
DIFFIO_TX105p
AB9
PISMO_NA23
B6
IO
DIFFIO_RX105n
AF4
PISMO_NA24
B6
IO
DIFFIO_RX105p
AF3
PISMO_NA25
B6
IO
DIFFIO_TX104n
AB6
PISMO_NA26
B6
IO
DIFFIO_TX110p
AD6
PISMO_NA3
B6
IO
DIFFIO_RX110n
AH4
PISMO_NA4
B6
IO
DIFFIO_RX110p
AH3
PISMO_NA5
B6
IO
DIFFIO_TX109n
AD9
PISMO_NA6
B6
IO
DIFFIO_TX109p
AD8
PISMO_NA7
B6
IO
DIFFIO_RX109n
AG4
PISMO_NA8
B6
IO
DIFFIO_RX109p
AG3
PISMO_NA9
Table 7-6. FPGA Pins Sorted by Signal Name (Continued)
Bank
Pin Type Name
Other Pin Information
Configuration
Function
Ball
Board Net
Содержание AT91CAP9
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