AT91CAP9A-DK Development Kit User Guide
3-15
6321B–CAP–02-Jul-07
85
B2
IO
DIFFIO_RX33p
L32
FPGA168
86
B2
IO
DIFFIO_RX33n
L31
FPGA169
87
GND
88
B2
IO
DIFFIO_TX33p
R23
FPGA170
89
GND
90
B2
IO
DIFFIO_TX33n
R22
FPGA171
91
B2
IO
DIFFIO_RX32p
N31
FPGA172
92
GND
93
B2
IO
DIFFIO_RX32n
N30
FPGA173
94
GND
95
B2
IO
DIFFIO_TX32p
R25
FPGA174
96
B2
CLK1p
INPUT
T30
FPGA175
97
GND
98
B2
IO
DIFFIO_RX31p
M32
FPGA176
99
GND
100
B2
IO
DIFFIO_RX31n
M31
FPGA177
101
B2
IO
DIFFIO_TX31p
R29
FPGA178
102
GND
103
B2
IO
DIFFIO_TX31n
R28
FPGA179
104
GND
105
B2
IO
DIFFIO_RX30p
P32
FPGA180
106
B2
IO
DIFFIO_RX30n
P31
FPGA181
107
GND
108
B2
IO
DIFFIO_TX30p
T28
FPGA182
109
GND
110
B2
IO
DIFFIO_TX30n
T27
FPGA183
111
B2
IO
DIFFIO_RX29p
R31
FPGA184
112
GND
113
B2
IO
DIFFIO_RX29n
R30
FPGA185
114
GND
115
B2
IO
DIFFIO_TX29p
T23
FPGA186
116
B2
IO
DIFFIO_TX29n
T22
FPGA187
117
GND
118
B2
IO
CLK0n/DIFFIO_RX_C0n
T31
FPGA188
119
GND
120
B2
IO
CLK0p/DIFFIO_RX_C0p
T32
FPGA189
Table 3-3. J10 (female) Pin Assignment Table (Continued)
J10 Pin
FPGA
Bank
FPGA Pin
Function
Other FPGA Pin
Information
FPGA Ball
Board Net
Содержание AT91CAP9
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