7-28
AT91CAP9A-DK Development Kit User Guide
6321B–CAP–02-Jul-07
GND
V15
GND
GND
V17
GND
GND
V19
GND
GND
V22
GND
GND
V27
GND
GNDA_PLL3
V8
GND
GND
W12
GND
GND
W14
GND
GND
W16
GND
GND
W18
GND
GND
W20
GND
GND
Y1
GND
GND
Y13
GND
GND
Y15
GND
GND
Y17
GND
GND
Y19
GND
GND
Y32
GND
VCCA_PLL6
AE15
VCCA_PLL
VCCA_PLL9
AE7
VCCA_PLL
VCCA_PLL12
AF18
VCCA_PLL
VCCA_PLL8
AF26
VCCA_PLL
VCCA_PLL5
G15
VCCA_PLL
VCCA_PLL11
H17
VCCA_PLL
VCCA_PLL7
H26
VCCA_PLL
VCCA_PLL10
H8
VCCA_PLL
VCCA_PLL4
R9
VCCA_PLL
VCCA_PLL1
T24
VCCA_PLL
VCCA_PLL3
U9
VCCA_PLL
VCCA_PLL2
V26
VCCA_PLL
VCCD_PLL6
AD15
VCCD_PLL
VCCD_PLL12
AE18
VCCD_PLL
VCCD_PLL9
AE8
VCCD_PLL
VCCD_PLL8
AF25
VCCD_PLL
VCCD_PLL5
H15
VCCD_PLL
VCCD_PLL7
H25
VCCD_PLL
VCCD_PLL10
H7
VCCD_PLL
Table 7-5. FPGA Pins Sorted by Bank/Signal Name (Continued)
Bank
Pin Type Name
Other Pin Information
Configuration
Function
Ball
Board Net
Содержание AT91CAP9
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