Analog Devices EZ-KIT Lite ADSP-BF506F, Справочник по аппаратуре

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ADSP-BF50x Blackfin Processor Hardware Reference 22-21
ADC Control Module (ACM)
The inactive period of
CS
(T
CSIW
as shown in the Figure 22-9 ) is the sum
of the three timing parameters – Setup Time (T
S
), Zero Time (T
Z
) and
the Hold Time (T
H
):
T
CSIW
= T
S
+ T
Z
+ T
H
.
Appropriate specification of the values of those three parameters can yield
the desired inactive period of
CS
.
In order to provide a predictable latency from the occurrence of an inter-
nal event to the assertion of an external ADC sampling event, the ADC
controls and
CS
must be driven on the rising edge of SCLK. Therefore, the
Setup Time (T
S
) of these signals is specified in terms of SCLK.
To achieve accurate timing relationship between
CS
and ACLK (which is a
free running clock), the ACLK signal is re-aligned with the active edge of
CS
. This realignment of ACLK ensures that the setup time of the first
active edge of ACLK, with respect to the active edge of
CS
, is at least
1 ACLK cycle.
The figures in the following sections:
• “Case 1—Chip Select Asserted During the High Phase of ACLK”
on page 22-22
• “Case 2—Chip Select Asserted During the Low Phase of ACLK”
on page 22-23
• “Case 3—Chip Select Asserted Right Before the Falling
Edge of ACLK” on page 22-24
• “Case 4—Chip Select Asserted Right Before the Rising
Edge of ACLK” on page 22-25
• “Case 5—ACLK Polarity Set to 1 (CLKPOL=1)” on page 22-26
show various scenarios of ACLK re-alignment. All of these figures assume
an ACLK:SCLK ratio of 1:4.