Xilinx VCU110, User Manual

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VCU110 Evaluation Board www.xilinx.com 18
UG1073 (v1.2) March 26, 2016
Chapter 1: VCU110 Evaluation Board Features
The VCU110 QDR2+ 18-bit SIO memory component interface adheres to the constraints
guidelines documented in the QDRII+ Design Guidelines section of the LogiCORE IP
UltraScale Architecture-Based FPGAs Memory Interface Solutions Product Guide V5.0 (PG150)
[Ref 3] for Vivado Design Suite. The VCU110 QDR2 memory component interface is a 40
Ω
impedance implementation.
For more details about the Cypress QDR2+ component memory, see the Cypress
CY7C2663KV18-550BZXC data sheet [Ref 21] .
RLD3 Component Memory
[ Figure 1-2 , callout 5]
The 1152 Mb RLD3 component memory system is comprised of two 576 Mb RLDRAM3
devices (Micron MT44K16M36RB-093E 36-bit and MT44K32M18RB-093E 18-bit) located at
U141 and U173. This memory system is connected to the XCVU190 HP banks 70, 71 and 72.
The RLD3 0.6V V
TT
termination voltage (net RLD3_VTERM_0V6) is sourced from TI
TPS51200DR linear regulator U143. The connections between RLD3 component memory
U141 and XCVU190 banks 70 and 71 are listed in Table 1-5 .
AV29 QDR2_18B_Q9 HSTL_I_DCI B2 Q9
AV28 QDR2_18B_Q10 HSTL_I_DCI D3 Q10
AU29 QDR2_18B_Q11 HSTL_I_DCI E3 Q11
AW26 QDR2_18B_Q12 HSTL_I_DCI F2 Q12
AU28 QDR2_18B_Q13 HSTL_I_DCI G3 Q13
AU27 QDR2_18B_Q14 HSTL_I_DCI K3 Q14
AT29 QDR2_18B_Q15 HSTL_I_DCI L2 Q15
AT27 QDR2_18B_Q16 HSTL_I_DCI N3 Q16
AT31 QDR2_18B_Q17 HSTL_I_DCI P3 Q17
AT30 QDR2_18B_CQ HSTL_I_DCI A11 CQ
AV26 QDR2_18B_CQ_B HSTL_I_DCI A1 CQ_B
NA NA NA P6 QVLD
Table 1-5: RLD3 Memory U141 36-bit I/F to FPGA U1 Banks 70 and 71
FPGA (U1) Pin Schematic Net Name I/O Standard
C27 RLD3_36B_DQ0 SSTL12
D29 RLD3_36B_DQ1 SSTL12
A29 RLD3_36B_DQ2 SSTL12
B27 RLD3_36B_DQ3 SSTL12
Table 1-4: QDR2 Memory U168 18-bit SIO I/F to FPGA U1 Banks 66 and 67 (Cont’d)
FPGA (U1) Pin Schematic Net Name I/O Standard Pin Number Pin Name
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