Xilinx VCU110, User Manual

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VCU110 Evaluation Board www.xilinx.com 109
UG1073 (v1.2) March 26, 2016
Chapter 1: VCU110 Evaluation Board Features
FPGA Mezzanine Card (FMC) Interface
[ Figure 1-2 , callouts 33, 34]
The VCU110 evaluation board supports the VITA 57.1 FPGA Mezzanine Card (FMC)
specification by providing subset implementations of high pin count connectors at J22
(HPC0) and J2 (HPC1). HPC connectors use a 10 x 40 form factor, populated with 400 pins.
The connectors are keyed so that a mezzanine card, when installed in either of these FMC
connectors on the VCU110 evaluation board, faces away from the board.
The Samtec connector system is rated for signaling speeds up to 9 GHz (18 Gb/s) based on
a –3 dB insertion loss point within a two-level signaling environment.
TX5_P K6 EXAMAX_TX5_P AT38 MGTYTXP3_120
GTY Quad 120
TX5_N L6 EXAMAX_TX5_N AT39 MGTYTXN3_120
RX5_P B6 EXAMAX_RX5_P AT43 MGTYRXP3_120
RX5_N C6 EXAMAX_RX5_N AT44 MGTYRXN3_120
TX6_P H6 EXAMAX_TX6_P AU40 MGTYTXP2_120
TX6_N I6 EXAMAX_TX6_N AU41 MGTYTXN2_120
RX6_P E6 EXAMAX_RX6_P AU45 MGTYRXP2_120
RX6_N F6 EXAMAX_RX6_N AU46 MGTYRXN2_120
TX7_P L7 EXAMAX_TX7_P AV38 MGTYTXP1_120
TX7_N M7 EXAMAX_TX7_N AV39 MGTYTXN1_120
RX7_P C7 EXAMAX_RX7_P AV43 MGTYRXP1_120
RX7_N D7 EXAMAX_RX7_N AV44 MGTYRXN1_120
TX8_P I7 EXAMAX_TX8_P AW40 MGTYTXP0_120
TX8_N J7 EXAMAX_TX8_N AW41 MGTYTXN0_120
RX8_P F7 EXAMAX_RX8_P AW45 MGTYRXP0_120
RX8_N G7 EXAMAX_RX8_N AW46 MGTYRXN0_120
Notes:
1. MGT connections I/O standard not applicable.
Table 1-55: VCU110 ExaMAX J116 to FPGA U1 GTY Quads 121-120 Connections (Cont’d)
ExaMAX
J116 Pin
Name
ExaMAX J116
Pin Number
Schematic Net
Name
(1)
FPGA (U1)
Pin
FPGA (U1) Pin
Name
MGT Quad
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