Xilinx VCU110, User Manual

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VCU110 Evaluation Board www.xilinx.com 16
UG1073 (v1.2) March 26, 2016
Chapter 1: VCU110 Evaluation Board Features
QDR2+ Component Memory
[ Figure 1-2 , callout 4]
The 144 Mb QDR2+ component memory system is comprised of one 18-bit separate I/O
(SIO) device (Cypress CY7C2663KV18-550BZXC) located at U168. This memory system is
connected to the XCVU190 HP banks 66 and 67. The DDR4 0.75V V
TT
termination voltage
(net QDR2_VTERM_0V75) is sourced from TI TPS51200DR linear regulator U167. The
connections between QDR2 component memory U168 and XCVU190 banks 66 and 67 are
listed in Table 1-4 .
HR Bank 84 VCC1V8_FPGA 1.8V
HR Bank 94 VCC1V8_FPGA 1.8V
Table 1-4: QDR2 Memory U168 18-bit SIO I/F to FPGA U1 Banks 66 and 67
FPGA (U1) Pin Schematic Net Name I/O Standard Pin Number Pin Name
AM23 QDR2_18B_D0 HSTL_I_DCI P10 D0
AM24 QDR2_18B_D1 HSTL_I_DCI N11 D1
AN23 QDR2_18B_D2 HSTL_I_DCI M11 D2
AP22 QDR2_18B_D3 HSTL_I_DCI K10 D3
AM26 QDR2_18B_D4 HSTL_I_DCI J11 D4
AN25 QDR2_18B_D5 HSTL_I_DCI G11 D5
AN26 QDR2_18B_D6 HSTL_I_DCI E10 D6
AP25 QDR2_18B_D7 HSTL_I_DCI D11 D7
AP23 QDR2_18B_D8 HSTL_I_DCI C11 D8
AU26 QDR2_18B_D9 HSTL_I_DCI B3 D9
AT26 QDR2_18B_D10 HSTL_I_DCI C3 D10
AR25 QDR2_18B_D11 HSTL_I_DCI D2 D11
AT24 QDR2_18B_D12 HSTL_I_DCI F3 D12
AR24 QDR2_18B_D13 HSTL_I_DCI G2 D13
AU22 QDR2_18B_D14 HSTL_I_DCI J3 D14
AT22 QDR2_18B_D15 HSTL_I_DCI L3 D15
AR22 QDR2_18B_D16 HSTL_I_DCI M3 D16
AR23 QDR2_18B_D17 HSTL_I_DCI N2 D17
BA22 QDR2_18B_A0 HSTL_I_DCI A3 A0
AY24 QDR2_18B_A1 HSTL_I_DCI A9 A1
AW23 QDR2_18B_A2 HSTL_I_DCI B4 A2
Table 1-3: I/O Bank Voltage Rails (Cont’d)
FPGA (U1) Bank Power Supply Rail Net Name Voltage
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