VCU110 Evaluation Board
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UG1073 (v1.2) March 26, 2016
Chapter 1:
VCU110 Evaluation Board Features
are accessible through an I2C interface connected to both the system controller and the
FPGA.
A Silicon Labs Si570 programmable low-jitter clock is used to provide a system clock for
FPGA designers. Through a UART (115200-8-N-1) text interface, the system clock (Si570)
can be set to any frequency between 10 MHz and 810 MHz. The Si570 defaults to a
power-on frequency of 156.25 MHz, but then automatically changes to the last saved
frequency setting requested by the user. Clock programming does not require FPGA
resources and may be set or adjusted prior to configuring the FPGA or after the FPGA has
been configured.
Additional functionality provided through the system controller UART2 is a text display of
the internal SYSMON registers for V
CCINT
, V
CCBRAM
, V
CCAUX
, and the UltraScale FPGA U1
device temperature.
Power rail voltages set by the Maxim controllers are also displayed through the UART2 for
VCCINT, VCC1V8, VADJ_1V8, VCC1V2, VCC1V5, HMC1V2, MGTAVCC, MGTAVTT,
MGTVCCAUX, UTIL_0V9, UTIL_1V35, and UTIL_3V3. Refer to
for PMBus accessible
voltage regulators.
The installation of the USB UART drivers is documented in
Appendix C, Getting Started with
.
