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Xilinx VCU110, User Manual

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Xilinx VCU110 User Manual Download Page 129

VCU110 Evaluation Board

www.xilinx.com

129

UG1073 (v1.2) March 26, 2016

Appendix A

Default Switch and Jumper Settings

The default switch and jumper settings for the VCU110 evaluation board are provided in 

this appendix.

Switches

Default switch settings are listed in 

Table A-1

.

Table A-1:

Default Switch Settings

Switch

Function

Default

Comments

Figure 1-2 

Callout

Schematic 

0381556 Page

SW1

SPST slide switch

Off

Board shipped with power switch 

off 

30

71

SW12

4-pole GPIO DIP switch

(1)

0000

POS 1-4 GPIO active-High

26

64

SW15

5-pole configuration

DIP switch

(1)

00000

POS 1-5 Zynq AP SoC

system controller U111

28

51

SW16

3-pole configuration

DIP switch

(1)

101

POS 1-3 FPGA U1 mode M[2:0]

35

3

Notes: 

1. DIP switches are active high (connected net is pulled high when DIP switch is closed).

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Summary of Contents for VCU110

Page 1: ...VCU110 Evaluation Board User Guide UG1073 v1 2 March 26 2016...

Page 2: ...PI Flash Memory Micro SD Card Interface and FMC HPC1 Connector J2 Updated Table 1 15 Table 1 16 Table 1 17 Table 1 18 Table 1 19 Table 1 20 Table 1 23 Table 1 24 Table 1 25 Table 1 40 and Table 1 59 A...

Page 3: ...n 36 System Clock 39 Programmable User Clock 41 Jitter Attenuating Clock Multipliers 42 User SMA Clock 45 GTY Transceivers 46 GTH Transceivers 61 PCI Express Endpoint Connectivity 76 CFP Module Quad C...

Page 4: ...1 FMC Connector Pinouts Overview 131 Appendix C Getting Started with System Controller Overview 132 Appendix D Master Constraints File Listing Overview 134 VCU110 Board Constraints File Listing 134 Ap...

Page 5: ...VCU110 Evaluation Board www xilinx com 5 UG1073 v1 2 March 26 2016 References 154 Please Read Important Legal Notices 156 Send Feedback...

Page 6: ...supported using VITA 57 FPGA mezzanine cards FMC attached to two high pin count HPC FMC connectors See Appendix H Additional Resources and Legal Notices for references to documents files and resource...

Page 7: ...nnector 52 GTH transceivers 13 Quads 8 Quads connected to HMC 2 Quads connected to FMC HPC0 connector DP 2 Quads connected to FMC HPC1 connector DP 1 Quad connected to PCIe cable connector Ethernet PH...

Page 8: ...lectrostatic discharge ESD Follow ESD prevention measures when handling the board X Ref Target Figure 1 1 Figure 1 1 VCU110 Evaluation Board Block Diagram 8VHU 60 ORFN 3DJH 4 5 ELW 3DJH 0 3 3 5 5 3 3...

Page 9: ...Feature Descriptions IMPORTANT The image in Figure 1 2 is for reference only and might not reflect the current revision of the board CAUTION The VCU110 evaluation board can be damaged by electrostatic...

Page 10: ...4 outputs 300 MHz 125 MHz 90 MHz 33 33 MHz 46 11 Programmable User Clock I2C programmable user clock LVDS U32 with 1 to 2 LVDS buffer U32 Silicon Labs SI570BAB0000544DG default 156 250MHz with Si5334...

Page 11: ...01M2S3AQE2 71 31 VCU110 Board Power System power management system top and bottom Maxim MAX15301 and MAX15303 digital POL controllers 72 86 32 Monitoring Voltage and Current power management voltage a...

Page 12: ...uration The VCU110 board supports two of the five UltraScale FPGA configuration modes Master SPI using the onboard dual Quad SPI QSPI flash memory JTAG using either USB JTAG configuration port Digilen...

Page 13: ...ly as shown in Figure 1 3 The FPGA default mode setting M 2 0 101 selecting the JTAG configuration mode For full details on configuring the FPGA see UltraScale Architecture Configuration User Guide UG...

Page 14: ...e output connected to the XCVU190 FPGA U1 VCCBATT pin AN13 The battery supply current IBATT specification is 150 nA maximum when board power is off B1 is charged from the SYS_1V8 1 8V rail through a s...

Page 15: ...HP HP 0 HP 66 65 U1 GTH224 GTH230 GTH229 GTH228 GTH227 GTH226 GTH225 67 HP 72 71 70 84 94 HP GTH232 GTH231 GTH220 GTH221 GTH222 GTH223 GTY124 GTY130 GTY129 GTY128 GTY127 GTY126 GTY125 GTY131 GTY121 G...

Page 16: ...U1 Pin Schematic Net Name I O Standard Pin Number Pin Name AM23 QDR2_18B_D0 HSTL_I_DCI P10 D0 AM24 QDR2_18B_D1 HSTL_I_DCI N11 D1 AN23 QDR2_18B_D2 HSTL_I_DCI M11 D2 AP22 QDR2_18B_D3 HSTL_I_DCI K10 D3 A...

Page 17: ...R88 A18 AV23 QDR2_18B_A19 HSTL_I_DCI R9 A19 AY25 QDR2_18B_A20 HSTL_I_DCI A10 NC_72M AY22 QDR2_18B_A21 HSTL_I_DCI A2 NC_144M AN24 QDR2_18B_BWS0_B HSTL_I_DCI B7 BWS0_BS0_B_B AT25 QDR2_18B_BWS1_B HSTL_I_...

Page 18: ...d to the XCVU190 HP banks 70 71 and 72 The RLD3 0 6V VTT termination voltage net RLD3_VTERM_0V6 is sourced from TI TPS51200DR linear regulator U143 The connections between RLD3 component memory U141 a...

Page 19: ...H27 RLD3_36B_DQ18 SSTL12 J27 RLD3_36B_DQ19 SSTL12 G26 RLD3_36B_DQ20 SSTL12 F29 RLD3_36B_DQ21 SSTL12 G28 RLD3_36B_DQ22 SSTL12 E27 RLD3_36B_DQ23 SSTL12 E29 RLD3_36B_DQ24 SSTL12 F26 RLD3_36B_DQ25 SSTL12...

Page 20: ...D3_36B_A8 SSTL12 B22 RLD3_36B_A9 SSTL12 C23 RLD3_36B_A10 SSTL12 G21 RLD3_36B_A13 SSTL12 F24 RLD3_36B_A14 SSTL12 A23 RLD3_36B_A17 SSTL12 B23 RLD3_36B_A18 SSTL12 C25 RLD3_36B_BA0 SSTL12 E24 RLD3_36B_BA1...

Page 21: ...STL12 K18 RLD3_18B_DQ6 SSTL12 M20 RLD3_18B_DQ7 SSTL12 K19 RLD3_18B_DQ8 SSTL12 N19 RLD3_18B_DQ9 SSTL12 M16 RLD3_18B_DQ10 SSTL12 M17 RLD3_18B_DQ11 SSTL12 N20 RLD3_18B_DQ12 SSTL12 P16 RLD3_18B_DQ13 SSTL1...

Page 22: ...t memory see the Micron MT44K16M36RB 093E MT44K32M18RB 093E data sheet Ref 22 A18 RLD3_18B_BA1 SSTL12 B20 RLD3_18B_BA2 SSTL12 G20 RLD3_18B_BA3 SSTL12 B18 RLD3_18B_WE_B SSTL12 C20 RLD3_18B_REF_B SSTL12...

Page 23: ...can be used for configuration and data storage Part number MT25QU512ABA8E12 0SIT Micron Supply voltage 1 8V Datapath width 8 bits Data rate various depending on Single Dual Quad mode Note For details...

Page 24: ...0 R349 2 1 R394 DNP DNP QSPI1_IO0 QSPI1_IO2 GND UTIL_3V3 UTIL_3V3 2 1 R875 4 7K 5 R309 1 2 2 40K 1 2 1 R874 4 7K 5 R310 1 2 2 40K 1 2 1 R893 4 7K 5 5 4 7K R894 1 2 NC NC NC NC NC NC NC NC NC NC NC NC...

Page 25: ...ads Table 1 7 Dual QSPI Memory U182 U183 I F to FPGA U1 Banks 0 and 65 FPGA U1 Pin Schematic Net Name I O Standard QSPI Memory Pin Number Pin Name Reference Designator AM14 QSPI0_IO0 1 D3 DQ0 U182 AK1...

Page 26: ...MC_L0TX_12_N G17 L0RXN_0 MGTHRXP0_229 R2 HMC_L0RX_12_C_P E24 L0TXP_0 MGTHRXN0_229 R1 HMC_L0RX_12_C_N E23 L0TXN_0 MGTHTXP1_229 P9 HMC_L0TX_9_P F19 L0RXP_1 MGTHTXN1_229 P8 HMC_L0TX_9_N F18 L0RXN_1 MGTHR...

Page 27: ...TX_0_P C22 L0RXP_6 MGTHTXN2_230 J6 HMC_L0TX_0_N C21 L0RXN_6 MGTHRXP2_230 J2 HMC_L0RX_0_C_P A20 L0TXP_6 MGTHRXN2_230 J1 HMC_L0RX_0_C_N A19 L0TXN_6 MGTHTXP3_230 H9 HMC_L0TX_1_P B23 L0RXP_7 MGTHTXN3_230...

Page 28: ...9 MGTHTXP2_231 G11 HMC_L0TX_6_P C30 L0RXP_10 MGTHTXN2_231 G10 HMC_L0TX_6_N C29 L0RXN_10 MGTHRXP2_231 G16 HMC_L0RX_6_C_P G22 L0TXP_10 MGTHRXN2_231 G15 HMC_L0RX_6_C_N G21 L0TXN_10 MGTHTXP3_231 F13 HMC_L...

Page 29: ...HMC_L0TX_5_P F27 L0RXP_14 MGTHTXN2_232 C6 HMC_L0TX_5_N F26 L0RXN_14 MGTHRXP2_232 C2 HMC_L0RX_5_C_P G30 L0TXP_14 MGTHRXN2_232 C1 HMC_L0RX_5_C_N G29 L0TXN_14 MGTHTXP3_232 A7 HMC_L0TX_7_P E28 L0RXP_15 M...

Page 30: ...AD17 L1RXN_0 MGTHRXP0_225 AL2 HMC_L1RX_0_C_P AF24 L1TXP_0 MGTHRXN0_225 AL1 HMC_L1RX_0_C_N AF23 L1TXN_0 MGTHTXP1_225 AK9 HMC_L1TX_2_P AE19 L1RXP_1 MGTHTXN1_225 AK8 HMC_L1TX_2_N AE18 L1RXN_1 MGTHRXP1_22...

Page 31: ...L1TX_7_P W28 L1RXP_9 MGTHTXN2_226 AE6 HMC_L1TX_7_N W27 L1RXN_9 MGTHRXP2_226 AE2 HMC_L1RX_7_C_P Y26 L1TXP_9 MGTHRXN2_226 AE1 HMC_L1RX_7_C_N Y25 L1TXN_9 MGTHTXP3_226 AD9 HMC_L1TX_5_P Y30 L1RXP_8 MGTHTXN...

Page 32: ...L1TXN_6 MGTHTXP2_227 AA7 HMC_L1TX_15_P AG21 L1RXP_5 MGTHTXN2_227 AA6 HMC_L1TX_15_N AG20 L1RXN_5 MGTHRXP2_227 AA2 HMC_L1RX_15_C_P AJ27 L1TXP_5 MGTHRXN2_227 AA1 HMC_L1RX_15_C_N AJ26 L1TXN_5 MGTHTXP3_22...

Page 33: ...7 HMC_L1TX_9_P AE19 L1RXP_1 MGTHTXN2_228 U6 HMC_L1TX_9_N AE18 L1RXN_1 MGTHRXP2_228 U2 HMC_L1RX_9_C_P AE23 L1TXP_1 MGTHRXN2_228 U1 HMC_L1RX_9_C_N AE22 L1TXN_1 MGTHTXP3_228 T9 HMC_L1TX_8_P AD18 L1RXP_0...

Page 34: ...r U111 and the micro SD card connector J83 Table 1 10 HMC Memory U160 Control I F Connections HMC U160 Pin Number HMC U160 Pin Name Schematic Net Name 1 I O Standard Connected Pin Number Connected Dev...

Page 35: ...les such as the Platform Cable USB II and the Parallel Cable IV JTAG initiated configuration takes priority over the configuration method selected through the FPGA mode pins M 2 0 wired to SW16 positi...

Page 36: ...debugger to access the FPGA The Xilinx configuration software tool can also program the dual Quad SPI Flash memory Clock Generation The VCU110 evaluation board provides fourteen clock sources to the...

Page 37: ...Two external input clocks through BULLSEYE2 connector J122 BULLSEYE2_GTY_REFCLK 0 1 _P N PCIe cable J136 Two external input clocks through PCIe cable J136 PCIE_CABLE_CLK_C_P N USER_SMA_CLOCK J34 P J35...

Page 38: ..._BUF2_C_N 2 3 R37 U196 30 ILKN_SI5328_OUT2_BUF3_C_P 2 3 N36 GTY 131 REFCLK0 U196 29 ILKN_SI5328_OUT2_BUF3_C_N 2 3 N37 U196 28 ILKN_SI5328_OUT2_BUF4_C_P 2 3 L36 GTY 132 REFCLK0 U196 27 ILKN_SI5328_OUT2...

Page 39: ...P N is a LVDS 300 MHz clock sourced from the CLK0A output pair of U122 The SYSCLK_300_P N pair is connected to XCVU190 FPGA U1 Bank 71 global clock GC pins J24 and H24 respectively Clock generator Sil...

Page 40: ...LVDS CLK_125MHZ_N CLK_125MHZ_P U122 7 24 20 16 15 11 22 21 18 17 14 10 13 9 6 25 12 19 8 1 5 3 2 XB RESET OEB_ALL XA LOS FS1 FS0 GNDPAD GND2 CLK3B CLK2B CLK3A CLK2A CLK1B CLK1A CLK0B CLK0A VDDO3 VDDO2...

Page 41: ...Hz User applications can change the output frequency within the range of 10 MHz to 810 MHz through an I2C interface Power cycling the VCU110 evaluation board resets the user clock to the default frequ...

Page 42: ...er X Ref Target Figure 1 10 Figure 1 10 HMC Jitter Attenuating Clock Multiplier GND GND GND GND GND HMC_SI5328_VCC L31 FERRITE 220 2 1 25V 0 1UF C23 2 1 C24 0 1UF 25V 2 1 C294 1UF 25V 2 1 HMC_SI5328_V...

Page 43: ...D GND Q0_P Q0_N CLK0_P CLK0_N CLK_SEL GNDPAD GND VDD VREF CLK1_P CLK1_N Q1_P Q1_N Q2_P Q2_N Q3_P Q3_N GND 2 1 1 100 R1484 1 2 1UF C2069 25V NC 9 10 6 7 2 17 1 5 8 3 4 11 12 13 14 15 16 SI53340 B GM QF...

Page 44: ...I5328_OUT1_P NC NC A1 A2_SS CKOUT2_N CKOUT2_P CMODE CS_CA GND1 GND2 GNDPAD LOL NC3 NC4 NC5 SCL SDA_SDO VDD3 RST_B NC1 INT_C1B C2B VDD1 XA XB NC2 VDD2 RATE0 CKIN2_P CKIN2_N RATE1 CKIN1_P CKIN1_N NC6 NC...

Page 45: ...CK_P and USER_SMA_CLOCK_N are connected to XCVU190 FPGA U1 VCCO 1 5V HP Bank 67 GC pins AY27 and AY28 respectively A 100 differential termination resistor is present on the board for these inputs The...

Page 46: ...to CFP4 connectors J107 J108 J109 and J110 respectively Two of the GTY Quads banks 124 and 126 are connected to BullsEye connectors J122 BULLSEYE2 and J87 BULLSEYE1 respectively Five of the GTY Quads...

Page 47: ...180 REFCLK1 not connected Four GTY transceivers allocated to CFP4_MOD2_TX RX 0 3 _P N J109 Quad 128 REFCLK0 CFP4_SI5328_OUT1_BUF4_C_P N U180 REFCLK1 CFP4_REC_CLOCK2_C_P N U179 Four GTY transceivers al...

Page 48: ...n Name Connected Device MGTYTXP0_120 BF38 EXAMAX_TX8_P I7 TX8_P ExaMAX J116 MGTYTXN0_120 BF39 EXAMAX_TX8_N J7 TX8_N MGTYRXP0_120 BF33 EXAMAX_RX8_P F7 RX8_P MGTYRXN0_120 BF34 EXAMAX_RX8_N G7 RX8_N MGTY...

Page 49: ..._N MGTYRXP1_121 BB43 EXAMAX_RX3_P C5 RX3_P MGTYRXN1_121 BB44 EXAMAX_RX3_N D5 RX3_N MGTYTXP2_121 BA40 EXAMAX_TX2_P H4 TX2_P MGTYTXN2_121 BA41 EXAMAX_TX2_N I4 TX2_N MGTYRXP2_121 BA45 EXAMAX_RX2_P E4 RX2...

Page 50: ...1N MGTYRXP1_122 AV43 CFP4_MOD0_RX2_P 36 RX2P RX2N MGTYRXN1_122 AV44 CFP4_MOD0_RX2_N 37 RX2N RX2P MGTYTXP2_122 AU40 CFP4_MOD0_TX1_P 48 TX1P TX2P MGTYTXN2_122 AU41 CFP4_MOD0_TX1_N 49 TX1N TX2N MGTYRXP2_...

Page 51: ...12 MGTYRXP1_124 AP43 BULLSEYE2_GTY_RX1_P 13 P13 MGTYRXN1_124 AP44 BULLSEYE2_GTY_RX1_N 14 P14 MGTYTXP2_124 AN40 BULLSEYE2_GTY_TX2_P 7 P7 MGTYTXN2_124 AN41 BULLSEYE2_GTY_TX2_N 8 P8 MGTYRXP2_124 AN45 BUL...

Page 52: ...1N MGTYRXP1_125 AK43 CFP4_MOD1_RX2_P 36 RX2P RX2N MGTYRXN1_125 AK44 CFP4_MOD1_RX2_N 37 RX2N RX2P MGTYTXP2_125 AJ40 CFP4_MOD1_TX1_P 48 TX1P TX2P MGTYTXN2_125 AJ41 CFP4_MOD1_TX1_N 49 TX1N TX2N MGTYRXP2_...

Page 53: ...2 MGTYRXP1_126 AF43 BULLSEYE1_GTY_RX1_P 13 P13 MGTYRXN1_126 AF44 BULLSEYE1_GTY_RX1_N 14 P14 MGTYTXP2_126 AE40 BULLSEYE1_GTY_TX2_P 7 P7 MGTYTXN2_126 AE41 BULLSEYE1_GTY_TX2_N 8 P8 MGTYRXP2_126 AE45 BULL...

Page 54: ...TX1N MGTYRXP1_127 AB43 CFP4_MOD2_RX2_P 36 RX2P RX2N MGTYRXN1_127 AB44 CFP4_MOD2_RX2_N 37 RX2N RX2P MGTYTXP2_127 AA40 CFP4_MOD2_TX1_P 48 TX1P TX2P MGTYTXN2_127 AA41 CFP4_MOD2_TX1_N 49 TX1N TX2N MGTYRX...

Page 55: ..._MOD3_RX2_P 36 RX2P RX2N MGTYRXN1_128 V44 CFP4_MOD3_RX2_N 37 RX2N RX2P MGTYTXP2_128 U40 CFP4_MOD3_TX1_P 48 TX1P TX2P MGTYTXN2_128 U41 CFP4_MOD3_TX1_N 49 TX1N TX2N MGTYRXP2_128 U45 CFP4_MOD3_RX1_P 33 R...

Page 56: ...KN_TX1_N C3 TX1_N MGTYRXP1_129 P43 ILKN_RX1_C_P 2 D2 RX1_P MGTYRXN1_129 P44 ILKN_RX1_C_N 2 D3 RX1_N MGTYTXP2_129 N40 ILKN_TX2_P A5 TX2_P MGTYTXN2_129 N41 ILKN_TX2_N A6 TX2_N MGTYRXP2_129 N45 ILKN_RX2_...

Page 57: ...KN_TX5_N C9 TX5_N MGTYRXP1_130 K43 ILKN_RX5_C_P 2 D8 RX5_P MGTYRXN1_130 K44 ILKN_RX5_C_N 2 D9 RX5_N MGTYTXP2_130 J40 ILKN_TX6_P F2 TX6_P MGTYTXN2_130 J41 ILKN_TX6_N F3 TX6_N MGTYRXP2_130 J45 ILKN_RX6_...

Page 58: ...H6 TX9_N MGTYRXP1_131 F43 ILKN_RX9_C_P 2 J5 RX9_P MGTYRXN1_131 F44 ILKN_RX9_C_N 2 J6 RX9_N MGTYTXP2_131 G36 ILKN_TX10_P F8 TX10_P MGTYTXN2_131 G37 ILKN_TX10_N F9 TX10_N MGTYRXP2_131 G31 ILKN_RX10_C_P...

Page 59: ...H12 TX13_N MGTYRXP1_132 D43 ILKN_RX13_C_P 2 J11 RX13_P MGTYRXN1_132 D44 ILKN_RX13_C_N 2 J12 RX13_N MGTYTXP2_132 C40 ILKN_TX14_P F14 TX14_P MGTYTXN2_132 C41 ILKN_TX14_N F15 TX14_N MGTYRXP2_132 C45 ILK...

Page 60: ...33 D34 ILKN_RX16_C_N 2 J15 RX16_N MGTYTXP1_133 C36 ILKN_TX17_P C11 TX17_P MGTYTXN1_133 C37 ILKN_TX17_N C12 TX17_N MGTYRXP1_133 C31 ILKN_RX17_C_P 2 D11 RX17_P MGTYRXN1_133 C32 ILKN_RX17_C_N 2 D12 RX17_...

Page 61: ...k for a Quad can be sourced from the Quad above or Quad below the GTH Quad of interest There are thirteen GTH Quads banks 220 232 on the VCU110 board with connectivity as shown here Quad 220 REFCLK0 n...

Page 62: ...t connected Four GTH transceivers allocated to HMC_L1 TX and RX 11 13 14 15 _P N U160 Quad 228 REFCLK0 not connected REFCLK1 not connected Four GTH transceivers allocated to HMC_L1 TX and RX 8 9 10 12...

Page 63: ...vice MGTHTXP0_220 BF9 FMC_HPC0_DP0_C2M_P C2 DP0_C2M_P FMC HPC0 J22 MGTHTXN0_220 BF8 FMC_HPC0_DP0_C2M_N C3 DP0_C2M_N MGTHRXP0_220 BF14 FMC_HPC0_DP0_M2C_P C6 DP0_M2C_P MGTHRXN0_220 BF13 FMC_HPC0_DP0_M2C...

Page 64: ...MC_HPC0_DP4_M2C_N A15 DP4_M2C_N MGTHTXP1_221 BB9 FMC_HPC0_DP5_C2M_P A38 DP5_C2M_P MGTHTXN1_221 BB8 FMC_HPC0_DP5_C2M_N A39 DP5_C2M_N MGTHRXP1_221 BB4 FMC_HPC0_DP5_M2C_P A18 DP5_M2C_P MGTHRXN1_221 BB3 F...

Page 65: ...A18 DP5_M2C_P MGTHRXN1_222 AV3 FMC_HPC1_DP5_M2C_N A19 DP5_M2C_N MGTHTXP2_222 AU7 FMC_HPC1_DP6_C2M_P B36 DP6_C2M_P MGTHTXN2_222 AU6 FMC_HPC1_DP6_C2M_N B37 DP6_C2M_N MGTHRXP2_222 AU2 FMC_HPC1_DP6_M2C_P...

Page 66: ...A2 DP1_M2C_P MGTHRXN1_224 AP3 FMC_HPC1_DP1_M2C_N A3 DP1_M2C_N MGTHTXP2_224 AN7 FMC_HPC1_DP2_C2M_P A26 DP2_C2M_P MGTHTXN2_224 AN6 FMC_HPC1_DP2_C2M_N A27 DP2_C2M_N MGTHRXP2_224 AN2 FMC_HPC1_DP2_M2C_P A...

Page 67: ...N1_225 AK8 HMC_L1TX_2_N AK15 L1RXN_2 MGTHRXP1_225 AK4 HMC_L1RX_2_C_P 2 AG17 L1TXP_2 MGTHRXN1_225 AK3 HMC_L1RX_2_C_N 2 AG16 L1TXN_2 MGTHTXP2_225 AJ7 HMC_L1TX_1_P AE19 L1RXP_1 MGTHTXN2_225 AJ6 HMC_L1TX_...

Page 68: ...3 MGTHRXP1_226 AF4 HMC_L1RX_3_C_P 2 AH18 L1TXP_3 MGTHRXN1_226 AF3 HMC_L1RX_3_C_N 2 AH17 L1TXN_3 MGTHTXP2_226 AE7 HMC_L1TX_7_P AJ23 L1RXP_7 MGTHTXN2_226 AE6 HMC_L1TX_7_N AJ22 L1RXN_7 MGTHRXP2_226 AE2 H...

Page 69: ...227 AB8 HMC_L1TX_14_N AE26 L1RXN_14 MGTHRXP1_227 AB4 HMC_L1RX_14_C_P 2 AD30 L1TXP_14 MGTHRXN1_227 AB3 HMC_L1RX_14_C_N 2 AD29 L1TXN_14 MGTHTXP2_227 AA7 HMC_L1TX_15_P AF28 L1RXP_15 MGTHTXN2_227 AA6 HMC_...

Page 70: ..._10 MGTHTXN1_228 V8 HMC_L1TX_10_N AH29 L1RXN_10 MGTHRXP1_228 V4 HMC_L1RX_10_C_P 2 AD22 L1TXP_10 MGTHRXN1_228 V3 HMC_L1RX_10_C_N 2 AD21 L1TXN_10 MGTHTXP2_228 U7 HMC_L1TX_9_P W28 L1RXP_9 MGTHTXN2_228 U6...

Page 71: ...9 MGTHTXN1_229 P8 HMC_L0TX_9_N M27 L0RXN_9 MGTHRXP1_229 P4 HMC_L0RX_9_C_P 2 L26 L0TXP_9 MGTHRXN1_229 P3 HMC_L0RX_9_C_N 2 L25 L0TXN_9 MGTHTXP2_229 N7 HMC_L0TX_13_P G26 L0RXP_13 MGTHTXN2_229 N6 HMC_L0TX...

Page 72: ...26 L0RXN_14 MGTHRXP1_230 K4 HMC_L0RX_14_C_P 2 G30 L0TXP_14 MGTHRXN1_230 K3 HMC_L0RX_14_C_N 2 G29 L0TXN_14 MGTHTXP2_230 J7 HMC_L0TX_0_P G18 L0RXP_0 MGTHTXN2_230 J6 HMC_L0TX_0_N G17 L0RXN_0 MGTHRXP2_230...

Page 73: ...TXN1_231 F8 HMC_L0TX_11_N D28 L0RXN_11 MGTHRXP1_231 F4 HMC_L0RX_11_C_P 2 C26 L0TXP_11 MGTHRXN1_231 F3 HMC_L0RX_11_C_N 2 C25 L0TXN_11 MGTHTXP2_231 G11 HMC_L0TX_6_P C22 L0RXP_6 MGTHTXN2_231 G10 HMC_L0TX...

Page 74: ...MGTHTXN1_232 E10 HMC_L0TX_15_N E27 L0RXN_15 MGTHRXP1_232 D4 HMC_L0RX_15_C_P 2 A28 L0TXP_15 MGTHRXN1_232 D3 HMC_L0RX_15_C_N 2 A27 L0TXN_15 MGTHTXP2_232 C7 HMC_L0TX_5_P D21 L0RXP_5 MGTHTXN2_232 C6 HMC_L...

Page 75: ...HRXN0_233 D13 PCIE_CABLE_RX3_N B12 PERN3 MGTHTXP1_233 C11 PCIE_CABLE_TX2_C_P 2 A8 PETP2 MGTHTXN1_233 C10 PCIE_CABLE_TX2_C_N 2 A9 PETN2 MGTHRXP1_233 C16 PCIE_CABLE_RX2_P B8 PERP2 MGTHRXN1_233 C15 PCIE_...

Page 76: ...f 27 Table 1 39 VCU110 PCIe Cable Connector J136 to FPGA U1 GTH Quad 233 Connections FPGA U1 Pin Name FPGA U1 Pin Schematic Net Name 1 Connected Pin Number Connected Pin Name Connected Device MGTHTXP0...

Page 77: ...GND 1 2 25V 0 1UF C1551 1 2 25V 22UF C1554 UTIL_3V3 1 2 25V 0 1UF C1553 1 2 25V 22UF C1556 L86 2 1 1UH 15A 20 J107 53 54 55 56 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29...

Page 78: ..._P 51 TX2P TX1P MGTYTXN1_122 AV39 CFP4_MOD0_TX2_N 52 TX2N TX1N MGTYRXP1_122 AV43 CFP4_MOD0_RX2_P 36 RX2P RX2N MGTYRXN1_122 AV44 CFP4_MOD0_RX2_N 37 RX2N RX2P MGTYTXP2_122 AU40 CFP4_MOD0_TX1_P 48 TX1P T...

Page 79: ...N TX1N MGTYRXP1_125 V43 CFP4_MOD1_RX2_P 36 RX2P RX2N MGTYRXN1_125 V44 CFP4_MOD1_RX2_N 37 RX2N RX2P MGTYTXP2_125 U40 CFP4_MOD1_TX1_P 48 TX1P TX2P MGTYTXN2_125 U41 CFP4_MOD1_TX1_N 49 TX1N TX2N MGTYRXP2_...

Page 80: ...N TX1N MGTYRXP1_127 P43 CFP4_MOD2_RX2_P 36 RX2P RX2N MGTYRXN1_127 P44 CFP4_MOD2_RX2_N 37 RX2N RX2P MGTYTXP2_127 N40 CFP4_MOD2_TX1_P 48 TX1P TX2P MGTYTXN2_127 N41 CFP4_MOD2_TX1_N 49 TX1N TX2N MGTYRXP2_...

Page 81: ...YTXN1_128 E37 CFP4_MOD3_TX2_N 52 TX2N TX1N MGTYRXP1_128 D43 CFP4_MOD3_RX2_P 36 RX2P RX2N MGTYRXN1_128 D44 CFP4_MOD3_RX2_N 37 RX2N RX2P MGTYTXP2_128 C40 CFP4_MOD3_TX1_P 48 TX1P TX2P MGTYTXN2_128 C41 CF...

Page 82: ...ettings can be over written using software commands passed over the MDIO interface Table 1 44 Board Connections for PHY Configuration Pins Pin Bit 2 Bit 1 Bit 0 Description Pin to Constant Mapping Pin...

Page 83: ...Y connections Table 1 45 FPGA U1 to Ethernet PHY U58 Connections FPGA U1 Pin Net Name I O Standard M88E111 PHY U58 Pin Name BB21 PHY_MDIO LVCMOS18 M1 MDIO_SDA BC18 PHY_MDC LVCMOS18 L3 MDC_SCL BC21 PHY...

Page 84: ...51 Ref 9 The product brief for the Marvell 88E1111 Alaska Gigabit Ethernet Transceiver can be found at the Marvell website Ref 30 The data sheet can be obtained under NDA with Marvell Contact informat...

Page 85: ...FPGA logic using IP like the LogiCORE IP AXI UART Lite v2 0 Product Guide for Vivado Design Suite PG142 Ref 10 I2C Bus Topology and Bus Switches Figure 1 2 callouts 21 22 The VCU110 evaluation board...

Page 86: ...ew IIC MUX1 IIC MUX2 Maxim power regulators FPGA SYS Controller SYS_1V8 IIC 1 UTIL_3V3 to SYS_1V8 SYS_1V8 to UTIL_3V3 MAXIM_CABLE_B PMBUS_ALERT UTIL_3V3 to VCC1V8_2A MAXIM_CABLE_B PMBUS_ALERT VCC1V8_2...

Page 87: ...I2C Bus IIC_MAIN Bus Switches 3 DQN 9 8 8 9 WR Y 6 9 9 8 9 WR Y 6 9 9 8 6 VWHP RQWUROOHU QT 3 6R DQN 9 7 WR XV 6ZLWFK 8 8 3 WR XV 6ZLWFK 86 5B6 B 2 B6 6 3257B 3 1 5B B6 6 1B 0 B6 B6 6 3 B6 B6 6 0 B6...

Page 88: ...010100 0x14 U160 HMC FPGA SYSMON I2 6 0b0110010 0x32 U1 BANK 65 PCA9544 4 channel bus switch NA 0b1110101 0x75 U80 PCA9544 PMBus regulators 0 0b0010000 0b0011000 0b1110000 0b1110110 0x10 x18 0x70 x76...

Page 89: ...ON DS31 GPIO_LED_7 DS32 GPIO_LED_6 DS33 GPIO_LED_5 DS34 DONE DS40 SYS_5VO ON DS42 SYSCTLR INIT DS43 SYSCTLR STATUS DS44 SYSCTLR DONE DS45 SYSCTLR ERROR DS46 SYS_1VO ON DS47 DDR4 C2 VTT ON DS48 RLD3 V...

Page 90: ...ition user DIP switch callout 26 GPIO_DIP_SW 3 0 SW12 User GPIO LEDs Figure 1 2 callout 23 Figure 1 18 shows the GPIO LED circuit X Ref Target Figure 1 18 Figure 1 18 User LEDs GND LED GRN SMT DS6 1 2...

Page 91: ...1 P4 P2 Pushbutton GND GND P3 P1 P4 P2 Pushbutton GND SW6 TL3301EF100QG 2 4 1 3 TL3301EF100QG SW7 2 4 1 3 SW8 TL3301EF100QG 2 4 1 3 TL3301EF100QG SW9 2 4 1 3 SW10 TL3301EF100QG 2 4 1 3 GPIO_SW_S GPIO_...

Page 92: ...aluation Board Features CPU Reset Pushbutton Figure 1 2 callout 25 Figure 1 20 shows the CPU reset pushbutton circuit X Ref Target Figure 1 20 Figure 1 20 CPU Reset Pushbutton GND P3 P1 P4 P2 Pushbutt...

Page 93: ...e High 1 N25 GPIO_LED_0 LVCMOS12 DS7 1 N22 GPIO_LED_1 LVCMOS12 DS6 1 M22 GPIO_LED_2 LVCMOS12 DS8 1 M26 GPIO_LED_3 LVCMOS12 DS9 1 M25 GPIO_LED_4 LVCMOS12 DS10 1 P24 GPIO_LED_5 LVCMOS12 DS33 1 N24 GPIO_...

Page 94: ...d from 3 3V to 1 2V with SN74AVC4T245 drivers U47 and U49 2 Pushbutton SW7 is level shifted from 1 2V to 1 8V with SN74AVCT245 driver U197 for the U111 Bank 501 connection Table 1 49 VCU110 GPIO Conne...

Page 95: ...Power System section for details on the onboard power system CAUTION Do NOT plug a PC ATX power supply 6 pin connector into J15 on the VCU110 evaluation board The ATX 6 pin connector has a different...

Page 96: ...r connector J15 power switch SW1 and indicator LED DS26 X Ref Target Figure 1 23 Figure 1 23 ATX Power Supply Adapter Cable To J15 on VCU110 Board X Ref Target Figure 1 24 Figure 1 24 Power On Off Swi...

Page 97: ...clears the FPGA programmable logic configuration The FPGA_PROG_B signal is connected to XCVU190 FPGA U1 pin AE14 For further configuration details see the UltraScale Series FPGAs Configuration User G...

Page 98: ...gure 1 26 BULLSEYE1 SMA Connector J87 GND NC NC BULLSEYE1_GTY_REFCLK0_P BULLSEYE1_GTY_REFCLK0_N BULLSEYE1_GTY_RX0_P BULLSEYE1_GTY_RX0_N BULLSEYE1_GTY_TX0_P BULLSEYE1_GTY_TX0_N BULLSEYE1_GTY_RX1_P BULL...

Page 99: ...1 BULLSEYE1_GTY_TX1_P AF38 MGTYTXP1_126 12 BULLSEYE1_GTY_TX1_N AF39 MGTYTXN1_126 13 BULLSEYE1_GTY_RX1_P AF43 MGTYRXP1_126 14 BULLSEYE1_GTY_RX1_N AF44 MGTYRXN1_126 7 BULLSEYE1_GTY_TX2_P AE40 MGTYTXP2_1...

Page 100: ...14 P13 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 Samtec J122 CCC J 020 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 BULLSEYE2_GTY_REFCLK0_P BULLSEYE2_GTY_REFCLK0_N BULLSEYE2_GTY_RX0_P B...

Page 101: ...11 BULLSEYE2_GTY_TX1_P AP38 MGTYTXP1_124 12 BULLSEYE2_GTY_TX1_N AP39 MGTYTXN1_124 13 BULLSEYE2_GTY_RX1_P AP43 MGTYRXP1_124 14 BULLSEYE2_GTY_RX1_N AP44 MGTYRXN1_124 7 BULLSEYE2_GTY_TX2_P AN40 MGTYTXP2...

Page 102: ...ures PCIe Cable Connector Figure 1 2 callout 16 The PCIe cable connector is connected to FPGA U1 GTH Quad 233 Figure 1 28 shows the J136 connector IMPORTANT The TX_P N pairs and the CLK_P N pair are s...

Page 103: ...or J136 MGTHTXN0_233 D8 PCIE_CABLE_TX3_C_N 2 A12 PETN3 MGTHRXP0_233 D14 PCIE_CABLE_RX3_P B11 PERP3 MGTHRXN0_233 D13 PCIE_CABLE_RX3_N B12 PERN3 MGTHTXP1_233 C11 PCIE_CABLE_TX2_C_P 2 A8 PETP2 MGTHTXN1_2...

Page 104: ...Name Interlaken J121 Pin Number Schematic Net Name 2 FPGA U1 Pin FPGA U1 Pin Name FPGA U1 Bank TX0_P A2 ILKN_TX0_P R40 MGTYTXP0_129 GTY Quad 129 TX0_N A3 ILKN_TX0_N R41 MGTYTXN0_129 RX0_P B2 ILKN_RX0...

Page 105: ...TYRXP3_130 RX7_N J3 ILKN_RX7_C_N 1 H44 MGTYRXN3_130 TX8_P F5 ILKN_TX8_P G40 MGTYTXP0_131 GTY Quad 131 TX8_N F6 ILKN_TX8_N G41 MGTYTXN0_131 RX8_P G5 ILKN_RX8_C_P 1 G45 MGTYRXP0_131 RX8_N G6 ILKN_RX8_C_...

Page 106: ...43 MGTYRXP3_132 RX15_N J15 ILKN_RX15_C_N 1 B44 MGTYRXN3_132 TX16_P A11 ILKN_TX16_P D38 MGTYTXP0_133 GTY Quad 133 TX16_N A12 ILKN_TX16_N D39 MGTYTXN0_133 RX16_P J14 ILKN_RX16_C_P 1 D33 MGTYRXP0_133 RX1...

Page 107: ...0_N A18 NA NA RX20_P B17 NA NA RX20_N B18 NA NA TX21_P C17 NA NA TX21_N C18 NA NA RX21_P D17 NA NA RX21_N D18 NA NA FC_TX_SYNC J17 ILKN_FC_TX_SYNC 3 AM19 IO_L3P_T0L_N4 65 FC_RX_SYNC J18 ILKN_FC_RX_SYN...

Page 108: ...et Name 1 FPGA U1 Pin FPGA U1 Pin Name MGT Quad TX1_P K4 EXAMAX_TX1_P AY38 MGTYTXP3_121 GTY Quad 121 TX1_N L4 EXAMAX_TX1_N AY39 MGTYTXN3_121 RX1_P B4 EXAMAX_RX1_P AY43 MGTYRXP3_121 RX1_N C4 EXAMAX_RX1...

Page 109: ...g environment TX5_P K6 EXAMAX_TX5_P AT38 MGTYTXP3_120 GTY Quad 120 TX5_N L6 EXAMAX_TX5_N AT39 MGTYTXN3_120 RX5_P B6 EXAMAX_RX5_P AT43 MGTYRXP3_120 RX5_N C6 EXAMAX_RX5_N AT44 MGTYRXN3_120 TX6_P H6 EXAM...

Page 110: ...ovides connectivity for up to 160 single ended or 80 differential user defined signals 10 GT transceivers 2 GT clocks 4 differential clocks 159 ground and 15 power connections FMC HPC0 Connector J22 F...

Page 111: ...4 FMC_HPC0_DP4_M2C_P 1 BC2 B13 FMC_HPC0_DP7_M2C_N 1 AY3 A15 FMC_HPC0_DP4_M2C_N 1 BC1 B16 FMC_HPC0_DP6_M2C_P 1 BA2 A18 FMC_HPC0_DP5_M2C_P 1 BB4 B17 FMC_HPC0_DP6_M2C_N 1 BA1 A19 FMC_HPC0_DP5_M2C_N 1 BB3...

Page 112: ...2 C11 FMC_HPC0_LA06_N LVDS BE30 D11 FMC_HPC0_LA05_P LVDS BC29 C14 FMC_HPC0_LA10_P LVDS AR32 D12 FMC_HPC0_LA05_N LVDS BC30 C15 FMC_HPC0_LA10_N LVDS AT32 D14 FMC_HPC0_LA09_P LVDS BC31 C18 NA NA D15 FMC_...

Page 113: ...A E6 NA NA F5 NA NA E7 NA NA F7 NA NA E9 NA NA F8 NA NA E10 NA NA F10 NA NA E12 NA NA F11 NA NA E13 NA NA F13 NA NA E15 NA NA F14 NA NA E16 NA NA F16 NA NA E18 NA NA F17 NA NA E19 NA NA F19 NA NA E21...

Page 114: ...08_P LVDS BE29 H10 FMC_HPC0_LA04_P LVDS BB32 G13 FMC_HPC0_LA08_N LVDS BF29 H11 FMC_HPC0_LA04_N LVDS BB33 G15 NA NA H13 FMC_HPC0_LA07_P LVDS BA31 G16 NA NA H14 FMC_HPC0_LA07_N LVDS BB31 G18 NA NA H16 N...

Page 115: ...ame I O Standard U1 FPGA Pin J22 FMC HPC0 Pin Schematic Net Name I O Standard U1 FPGA Pin J2 NA NA K1 NA NA J3 NA NA K4 NA NA J6 NA NA K5 NA NA J7 NA NA K7 NA NA J9 NA NA K8 NA NA J10 NA NA K10 NA NA...

Page 116: ...1_DP3_M2C_N 1 AM3 B12 FMC_HPC1_DP7_M2C_P 1 AT4 A14 FMC_HPC1_DP4_M2C_P 1 AW2 B13 FMC_HPC1_DP7_M2C_N 1 AT3 A15 FMC_HPC1_DP4_M2C_N 1 AW1 B16 FMC_HPC1_DP6_M2C_P 1 AU2 A18 FMC_HPC1_DP5_M2C_P 1 AV4 B17 FMC_...

Page 117: ...9 FMC_HPC1_LA01_CC_N LVCMOS18 AT35 C11 FMC_HPC1_LA06_N LVCMOS18 AT36 D11 FMC_HPC1_LA05_P LVCMOS18 BC29 C14 FMC_HPC1_LA10_P LVCMOS18 AR32 D12 FMC_HPC1_LA05_N LVCMOS18 AU32 C15 FMC_HPC1_LA10_N LVCMOS18...

Page 118: ...M2C LVCMOS18 BA21 E3 NA NA F4 NA NA E6 NA NA F5 NA NA E7 NA NA F7 NA NA E9 NA NA F8 NA NA E10 NA NA F10 NA NA E12 NA NA F11 NA NA E13 NA NA F13 NA NA E15 NA NA F14 NA NA E16 NA NA F16 NA NA E18 NA NA...

Page 119: ...1_LA03_P LVCMOS18 AV36 H7 FMC_HPC1_LA02_P LVCMOS18 AR34 G10 FMC_HPC1_LA03_N LVCMOS18 AW36 H8 FMC_HPC1_LA02_N LVCMOS18 AT34 G12 FMC_HPC1_LA08_P LVCMOS18 AN32 H10 FMC_HPC1_LA04_P LVCMOS18 AP33 G13 FMC_H...

Page 120: ...Schematic Net Name I O Standard U1 FPGA Pin J2 FMC HPC1 Pin Schematic Net Name I O Standard U1 FPGA Pin J2 NA NA K1 NA NA J3 NA NA K4 NA NA J6 NA NA K5 NA NA J7 NA NA K7 NA NA J9 NA NA K8 NA NA J10 N...

Page 121: ...TAVTT Regulator 45A Page 84 MGTVCCAUX Regulator 1A SYS_5V0 Regulator 1A Page 89 SYS_1V0 Regulator 2A Page 89 SYS_2V5 Regulator 2A 12VDC Page 74 Page 80 VCC1V5 Regulator 6A Page 81 HMC1V2 Regulator 20A...

Page 122: ...PGA 1 20V 79 MAX15301 U187 0x15 Maxim InTune digital POL controller 6A VCC1V5_FPGA 1 00V 80 MAX20751EKX U192 0x71 Maxim multiphase master with smart slave VT1697SBFQX 20A HMC1V2 1 20V 81 MAX20751EKX U...

Page 123: ...the Maxim website Ref 37 The associated Maxim PowerTool GUI is also downloadable from this Maxim site This is the simplest and most convenient way to monitor the voltage and current values for the po...

Page 124: ...l Figure 1 30 shows the SYSMON external multiplexer U75 circuit block diagram X Ref Target Figure 1 30 Figure 1 30 SYSMON External Multiplexer Block Diagram 7 3 5 3RUW SDQGHU 8 3 3 3 8 3 1 3 1 3 1 6 6...

Page 125: ...ON or MAXIM GUI NA I NA 0 10A 0 005 U119 20 0 1V VADJ_1V8_SYSMON_CS_P 23 S5A 100 VADJ_1V8_SYSMON_CS_N 7 S5B VCC1V2_FPGA MAX15301 U4 V 1 20V NA NA MAXIM GUI only NA I NA 0 10A 0 005 U120 20 0 1V VCC1V2...

Page 126: ...pins are dual purpose When pulled to GND through 20 5 k resistors the default SYSMON I2C address is set pre configuration The VCU110 implements 2 pin male headers J80 J81 which can be jumpered to thes...

Page 127: ...devices over an I2C interface The Zynq 7000 AP SoC system controller IP is not provided and is not available to end users for modification purposes The system controller is an ease of use feature tha...

Page 128: ...y setting requested by the user Clock programming does not require FPGA resources and may be set or adjusted prior to configuring the FPGA or after the FPGA has been configured Additional functionalit...

Page 129: ...ch Settings Switch Function Default Comments Figure 1 2 Callout Schematic 0381556 Page SW1 SPST slide switch Off Board shipped with power switch off 30 71 SW12 4 pole GPIO DIP switch 1 0000 POS 1 4 GP...

Page 130: ...mper Function Default Comments Figure A 1 Callout Schematic 0381556 Page J5 POR override 2 3 U1 POR_OVERRIDE pin P7 to GND 1 3 J12 Maxim regulator inhibit Off Used when programming power system 2 71 J...

Page 131: ...GND HA16_P LA09_N LA10_N GND DP4_M2C_N 16 HA17_P_CC HA14_N LA11_P LA12_N HA15_P HA16_N GND GND DP6_M2C_P GND 17 HA17_N_CC GND LA11_N GND HA15_N GND LA13_P GND DP6_M2C_N GND 18 GND HA18_P GND LA16_P GN...

Page 132: ...monitoring PMBus UltraScale FPGA system monitor SYSMON Adjustable FMC expansion interface voltage GPIO pushbuttons and configuration DIP switch UltraScale FPGA Configuration On power up the system con...

Page 133: ...on the PC desktop In the New connection dialog box click the serial radio button and then click the drop down arrow to open the list of ports Select the COM port with the Enhanced description Click O...

Page 134: ...d to 1 8V VADJ banks Because different FMC cards implement different circuitry the FMC bank I O standards must be uniquely defined by each customer IMPORTANT The VCU110 constraints XDC file can be fou...

Page 135: ...t_property PACKAGE_PIN AJ37 get_ports CFP4_SI5328_OUT1_BUF1_C_N set_property PACKAGE_PIN AJ36 get_ports CFP4_SI5328_OUT1_BUF1_C_P set_property PACKAGE_PIN AE37 get_ports CFP4_SI5328_OUT1_BUF2_C_N set_...

Page 136: ...PACKAGE_PIN BF22 get_ports QDR2_18B_A10 set_property IOSTANDARD HSTL_I_DCI get_ports QDR2_18B_A10 set_property PACKAGE_PIN BF21 get_ports QDR2_18B_A11 set_property IOSTANDARD HSTL_I_DCI get_ports QDR2...

Page 137: ...s QDR2_18B_D16 set_property PACKAGE_PIN AR23 get_ports QDR2_18B_D17 set_property IOSTANDARD HSTL_I_DCI get_ports QDR2_18B_D17 set_property PACKAGE_PIN AN28 get_ports QDR2_18B_Q0 set_property IOSTANDAR...

Page 138: ...orts RLD3_18B_A0 set_property IOSTANDARD SSTL12 get_ports RLD3_18B_A0 set_property PACKAGE_PIN F20 get_ports RLD3_18B_A3 set_property IOSTANDARD SSTL12 get_ports RLD3_18B_A3 set_property PACKAGE_PIN E...

Page 139: ...17 get_ports RLD3_18B_DQ15 set_property IOSTANDARD SSTL12 get_ports RLD3_18B_DQ15 set_property PACKAGE_PIN P20 get_ports RLD3_18B_DQ16 set_property IOSTANDARD SSTL12 get_ports RLD3_18B_DQ16 set_proper...

Page 140: ...2 get_ports RLD3_36B_A14 set_property PACKAGE_PIN A23 get_ports RLD3_36B_A17 set_property IOSTANDARD SSTL12 get_ports RLD3_36B_A17 set_property PACKAGE_PIN B23 get_ports RLD3_36B_A18 set_property IOST...

Page 141: ...LD3_36B_DQ22 set_property PACKAGE_PIN E27 get_ports RLD3_36B_DQ23 set_property IOSTANDARD SSTL12 get_ports RLD3_36B_DQ23 set_property PACKAGE_PIN E29 get_ports RLD3_36B_DQ24 set_property IOSTANDARD SS...

Page 142: ...LD1 set_property IOSTANDARD SSTL12 get_ports RLD3_36B_QVLD1 set_property PACKAGE_PIN F25 get_ports RLD3_36B_CK_N set_property IOSTANDARD DIFF_SSTL12 get_ports RLD3_36B_CK_N set_property PACKAGE_PIN G2...

Page 143: ...LA00_CC_N set_property IOSTANDARD LVDS get_ports FMC_HPC0_LA00_CC_N set_property PACKAGE_PIN AY32 get_ports FMC_HPC0_LA01_CC_P set_property IOSTANDARD LVDS get_ports FMC_HPC0_LA01_CC_P set_property PA...

Page 144: ...orts FMC_HPC1_CLK0_M2C_N set_property IOSTANDARD LVDS get_ports FMC_HPC1_CLK0_M2C_N set_property PACKAGE_PIN AV33 get_ports FMC_HPC1_LA00_CC_P set_property IOSTANDARD LVDS get_ports FMC_HPC1_LA00_CC_P...

Page 145: ...DARD LVCMOS12 get_ports MDIO_CFP4 CFP4 MOD0 set_property PACKAGE_PIN AN15 get_ports RX_LOS_MOD0_CFP4_LS set_property IOSTANDARD LVCMOS18 get_ports RX_LOS_MOD0_CFP4_LS set_property PACKAGE_PIN BF26 get...

Page 146: ...ty PACKAGE_PIN BA19 get_ports SGMII_TX_P set_property IOSTANDARD LVDS get_ports SGMII_TX_P set_property PACKAGE_PIN BB19 get_ports SGMII_TX_N set_property IOSTANDARD LVDS get_ports SGMII_TX_N set_prop...

Page 147: ...ports SYSMON_MUX_ADDR0_LS set_property IOSTANDARD LVCMOS12 get_ports SYSMON_MUX_ADDR0_LS set_property PACKAGE_PIN L21 get_ports SYSMON_MUX_ADDR1_LS set_property IOSTANDARD LVCMOS12 get_ports SYSMON_MU...

Page 148: ...perty IOSTANDARD LVCMOS12 get_ports PMOD0_0_LS set_property PACKAGE_PIN J22 get_ports PMOD0_1_LS set_property IOSTANDARD LVCMOS12 get_ports PMOD0_1_LS set_property PACKAGE_PIN J21 get_ports PMOD0_2_LS...

Page 149: ...linx com 149 UG1073 v1 2 March 26 2016 Appendix D Master Constraints File Listing 1 8V POWER GOOD set_property PACKAGE_PIN AP18 get_ports VADJ_1V8_PGOOD_LS set_property IOSTANDARD LVCMOS18 get_ports V...

Page 150: ...016 Appendix E Board Setup See the VCU110 Board Interface Test Tutorial on xilinx com vcu110 to get started using the evaluation board This tutorial provides instructions for setting up the board to t...

Page 151: ...Board Specifications Dimensions Height 8 50 inches 21 590 centimeters Thickness 10 0 150 inch 0 381 cm Length 14 45 inches 36 7 centimeters Environmental Temperature Operating 0 C to 45 C Storage 25 C...

Page 152: ...standards described in this section Refer to the VCU110 board master answer record concerning the CE requirements for the PC Test Environment VCU110 Evaluation Kit Master Answer Record AR 62604 Declar...

Page 153: ...this product can cause radio interference in which case the user might be required to take adequate measures Safety IEC 60950 1 2005 Information technology equipment Safety Part 1 General requirements...

Page 154: ...information related to the VCU107 board and its documentation is available on the following websites VCU110 Evaluation Kit VCU110 Evaluation Kit Master Answer Record AR 62604 These Xilinx documents p...

Page 155: ...C Packaging and Pinout Product Specification UG865 19 Silicon Labs CP210x USB to UART Installation Guide UG1033 20 Tera Term Terminal Emulator Installation Guide UG1036 For additional documents associ...

Page 156: ...sequential loss or damage including loss of data profits goodwill or any type of loss or damage suffered as a result of any action brought by a third party even if such damage or loss was reasonably f...

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