VIPA IM 253 DP Series, Manual, Page: 46 / 100

Chapter 3 Deployment IM 253DP Manual VIPA System 200V
3-6 HB97E - IM - RE_253-xDPxx - Rev. 12/44
A V-bus cycle (V-Bus = VIPA backplane bus) saves all the input data from
the modules in the PII and all the output data from the PIQ in the output
modules. When the data has been saved the PII is transferred into the
”buffer send” and the contents of the ”buffer receive” is transferred into PIQ.
During a PROFIBUS cycle the master addresses all its slaves according to
the sequence defined in the data exchange. The data exchange reads and
writes data from/into the memory areas assigned to the PROFIBUS.
The contents of the PROFIBUS input area is entered into the ”buffer
receive” and the data in the ”buffer send” is transferred into the PROFIBUS
output area.
The exchange of data between DP master and DP slave is completed
cyclically and it is independent from the V-bus cycle.
To ensure that the data transfer is synchronized the V-bus cycle time
should always be less than or equal to the DP cycle time.
The parameter min_slave_interval = 3ms is located in the GSD-file
(VIPA_0550.gsd).
In an average system it is guaranteed that the PROFIBUS data on the V-
bus is updated after a max. time of 3ms. You can therefore exchange data
with the slave at intervals of 3ms.
Note!
Starting with release version 6, the RUN-LED of a DP-V0 slave
extinguishes as soon as the V-Bus cycle lasts longer than the DP cycle.
This function is de-activated at the employment of a DP-V1 slave as
DP-V0.
V-bus cycle
DP cycle
V-bus cycle
≤≤≤≤
DP cycle