US Utah-400, Setup And Operation, Page: 138 / 157

The Debug Port
B-4
The Debug Port
•
On the Hyper-Terminal window select “File”, click on “Properties”.
•
Click the “Settings Tab” in the Properties Window.
•
Click the “ ASCII Setup ” Button.
•
In the “ASCII Receiving Block” at the bottom of the window, checkmark (enable) the
“ Append Line Feed to Incoming Line Ends ” and “ Wrap Lines that Exceed Terminal
Width ”. These parameters perform the same function as the Terminal’s CRLF Setting.
Using the Debug Port
The debug port is the RJ-45 female connector labeled J1, located on the left hand side of the
crosspoint. Its capabilities include:
CAUTION: Because this connection is located back from the board edge, the
locking mechanism on a standard RJ-45 connector will be difficult to disengage.
It is recommended that the locking tab be removed from the RJ-45 connector
before connecting it to J1.
•
System Power Up Display
•
Main Menu Display.
•
Verifying the FPGA Memory Status .
•
Verifying the Software Version .
•
Checking the Router Crosspoint Status to verify switching.
•
Checking the I / O Card Information .
•
Checking the Hardware Status .
Only the “Active” FPGA Control board will be read by the Debug Port. By pressing the “Reset”
button on the currently active FPGA board, the control should be transferred to the inactive
board.
If both FPGA’s are to be checked, be sure to press the “Reset” button after reading the first
board.
Caution: Resetting the control card will cause a brief interruption of all Audio/
Video paths in the system.