
5-12
SECTION 5
TEST RESULTS
5.3 ERRORS CATEGORY
BIT ERRORS
Bit Errors
— A count of received bits which
have a value opposite that of the corresponding
transmitted bits (one or zero) after pattern syn-
chronization is achieved.
BIT ERR SEC
Bit Errored Seconds
— A count of test seconds
where one or more bit errors occurred.
BIT ERR RT
Bit Error Rate
— The ratio of detected bit errors
to the number of data bits after pattern synchro-
nization is achieved.
CRC ERRORS
Cyclic Redundancy Check (CRC) Errors
—
A count of CRC errors detected. CRC errors are
counted only when ESF framing is present in the
received T1 data.
CRC ERR SEC
CRC Errored Seconds
— A count of seconds
within which one or more CRC errors are de-
tected.
CRC ERR RT
CRC Error Rate
— A count of CRC errors
divided by the total number of ESF superframes
analyzed.
Summary of Contents for T-BERD 107A
Page 81: ...SECTION 3 3 42 INSTRUMENT DESCRIPTION ...
Page 203: ...6 20 SECTION 6 PRINTER OPERATION ...
Page 239: ...C 18 STRESS PATTERNS APPENDIX C ...
Page 249: ...INTELLIGENT APPENDIX D NETWORK EQUIPMENT D 10 ...
Page 261: ...INDEX T BERD 107A INDEX 12 ...