⎯
200
⎯
6
F
2
S
0
8
3
5
Characteristic B is expressed by the following equation,
Iout
≤
DIFI2
where, DIFI1 and DIFI2 are setting values.
•
Set the charging current compensation DIFIC to zero.
•
Press 4 (= Logic circuit) on the "Test" sub-menu screen to display the "Logic circuit" screen.
•
Enter a signal number 41 to observe the DIF-A output at monitoring jack A and press the
ENTER key.
•
Apply a fixed infeed current to one relay. Apply an outflow current to another relay, change
the magnitude of the current applied and measure the value at which the element operates.
•
Repeat the above by changing the magnitude of the infeed current.
•
Check that the measured value of the outflow current is within
±
7% of the theoretical values
obtained using the equations mentioned above. (The infeed current is more than 0.5
×
In).
6.5.1.2 Residual current differential element DIFG
The residual current differential element is checked on the operating current and percentage
restraining characteristic in the same way as described in Section 6.5.1.1.
Element Signal
number
DIFG 44
The differences from the procedure described in Section 6.5.1.1 are as follows.
•
Apply a test current to terminal 7 and 8 instead of 1 and 2.
•
Enter a signal number 44 instead of 41 to observe the DIFG element operation at monitoring
jack A.
•
Use the settings DIFGI instead of DIFI1.
Summary of Contents for GRL100-101A
Page 223: ... 222 6 F 2 S 0 8 3 5 ...
Page 228: ... 227 6 F 2 S 0 8 3 5 Appendix B Signal List ...
Page 256: ... 255 6 F 2 S 0 8 3 5 Appendix C Variable Timer List ...
Page 258: ... 257 6 F 2 S 0 8 3 5 Appendix D Binary Output Default Setting List ...
Page 269: ... 268 6 F 2 S 0 8 3 5 ...
Page 270: ... 269 6 F 2 S 0 8 3 5 Appendix E Details of Relay Menu ...
Page 279: ... 278 6 F 2 S 0 8 3 5 ...
Page 288: ... 287 6 F 2 S 0 8 3 5 Appendix G Typical External Connection ...
Page 326: ... 325 6 F 2 S 0 8 3 5 Appendix J Return Repair Form ...
Page 330: ... 329 6 F 2 S 0 8 3 5 Customer Name Company Name Address Telephone No Facsimile No Signature ...
Page 331: ... 330 6 F 2 S 0 8 3 5 ...
Page 332: ... 331 6 F 2 S 0 8 3 5 Appendix K Technical Data ...
Page 343: ... 342 6 F 2 S 0 8 3 5 ...
Page 344: ... 343 6 F 2 S 0 8 3 5 Appendix L Symbols Used in Scheme Logic ...
Page 347: ... 346 6 F 2 S 0 8 3 5 ...
Page 348: ... 347 6 F 2 S 0 8 3 5 Appendix M Multi phase Autoreclose ...
Page 351: ... 350 6 F 2 S 0 8 3 5 ...
Page 352: ... 351 6 F 2 S 0 8 3 5 Appendix N Data Transmission Format ...
Page 358: ... 357 6 F 2 S 0 8 3 5 Appendix O Example of DIF and DIFG Setting ...
Page 364: ... 363 6 F 2 S 0 8 3 5 Appendix Q IEC60870 5 103 Interoperability ...
Page 377: ... 376 6 F 2 S 0 8 3 5 ...
Page 378: ... 377 6 F 2 S 0 8 3 5 Appendix R Failed Module Tracing and Replacement ...
Page 384: ... 383 6 F 2 S 0 8 3 5 Appendix S PLC Setting Sample ...
Page 386: ... 385 6 F 2 S 0 8 3 5 Appendix T Ordering ...
Page 392: ......