⎯
231
⎯
6
F
2
S
0
8
3
5
Signal list
241
242
243
244
245
246
247
248
249
250
251 CHECKING
During automatic checking
252 CHK FAIL-Q
Fail-to-operate of tripping output circuit
253 CHK STEP1
Checking step1
254 CHK_STEP2
Checking step2
255 CHK_STEP3
Checking step3
256 OC/OCI_TRIP
OC/OCI trip
257 EF/EFI TRIP
EF/EFI trip
258 RYIDSV1
RYIDSV1 (Remote 1 relay address monitoring)
259 RYIDSV2
RYIDSV2 (Remote 2 relay address monitoring)
260
261 TRIP-H
Trip signal hold
262
263 DEG ALARM
DEG ALARM output
264 AMP ALARM
AMP ALARM output
265 DEG_OK
DEG OK output
266 CF1
Telecommunication failure detect signal for ch#1
267 CF2
Telecommunication failure detect signal for ch#2
268 TDSV1
Telecommunication delay time over of ch#1
269 TDSV2
Telecommunication delay time over of ch#2
270 50/60Hz
Pulse signal for end-to-end test
271 1PPS_OFF
1PPS signal check (instant)
272 1PPS_SV-L
1PPS signal check for a certain time at local term.
273 1PPS_SV-R
1PPS signal check for a certain time at remote term.
274 1PPS ERROR
1PPS signal interval error
275
276
277
278
ch2 used for sampling synchoronization
279 DIF#1_
DIF#1 element block signal
280 DIF#2
DIF#2 element block signal
281 DIF-A#1
DIF-A#1 element output
282 DIF-B#1
DIF-B#1 element output
283 DIF-C#1
DIF-C#1 element output
284 DIFG#1
DIFG#1 element output
285 DIF-A#2
DIF-A#2 element output
286 DIF-B#2
DIF-B#2 element output
287 DIF-C#2
DIF-C#2 element output
288 DIFG#2
DIFG#2 element output
289 OVER_PH
Phase difference (over)
290 INVALID_PH
Phase difference (invalid)
291 UNDER PH
Phase difference (under)
292
293
294
295 MODE2A
Synchronisation in MODE2A
296
297
298
299
300
301 OCMF-L1
OCMF-L1 element output
302 OCMF-L2
OCMF-L2 element output
303 OCMF-L3
OCMF-L3 element output
304 OCMF-L4
OCMF-L4 element output
305 OCMF-L5
OCMF-L5 element output
306 OCMF-L6
OCMF-L6 element output
307 OCMF-L7
OCMF-L7 element output
308 OCMF
OCMF element output “OR”
309 OCDF-A
OCDF-A element output
310 OCDF-B
OCDF-B element output
311 OCDF-C
OCDF-C element output
312 OVL-A
OVL-A element output (for 3phase line voltage)
313 OVL-B
OVL-B element output (for 3phase line voltage)
314 OVL-C
OVL-C element output (for 3phase line voltage)
315
316 EFF
EFF element output
317 UVSF-AB
UVSF-A element output
318 UVSF-BC
UVSF-B element output
319 UVSF-CA
UVSF-C element output
320
No.
Signal Name
Contents
Summary of Contents for GRL100-101A
Page 223: ... 222 6 F 2 S 0 8 3 5 ...
Page 228: ... 227 6 F 2 S 0 8 3 5 Appendix B Signal List ...
Page 256: ... 255 6 F 2 S 0 8 3 5 Appendix C Variable Timer List ...
Page 258: ... 257 6 F 2 S 0 8 3 5 Appendix D Binary Output Default Setting List ...
Page 269: ... 268 6 F 2 S 0 8 3 5 ...
Page 270: ... 269 6 F 2 S 0 8 3 5 Appendix E Details of Relay Menu ...
Page 279: ... 278 6 F 2 S 0 8 3 5 ...
Page 288: ... 287 6 F 2 S 0 8 3 5 Appendix G Typical External Connection ...
Page 326: ... 325 6 F 2 S 0 8 3 5 Appendix J Return Repair Form ...
Page 330: ... 329 6 F 2 S 0 8 3 5 Customer Name Company Name Address Telephone No Facsimile No Signature ...
Page 331: ... 330 6 F 2 S 0 8 3 5 ...
Page 332: ... 331 6 F 2 S 0 8 3 5 Appendix K Technical Data ...
Page 343: ... 342 6 F 2 S 0 8 3 5 ...
Page 344: ... 343 6 F 2 S 0 8 3 5 Appendix L Symbols Used in Scheme Logic ...
Page 347: ... 346 6 F 2 S 0 8 3 5 ...
Page 348: ... 347 6 F 2 S 0 8 3 5 Appendix M Multi phase Autoreclose ...
Page 351: ... 350 6 F 2 S 0 8 3 5 ...
Page 352: ... 351 6 F 2 S 0 8 3 5 Appendix N Data Transmission Format ...
Page 358: ... 357 6 F 2 S 0 8 3 5 Appendix O Example of DIF and DIFG Setting ...
Page 364: ... 363 6 F 2 S 0 8 3 5 Appendix Q IEC60870 5 103 Interoperability ...
Page 377: ... 376 6 F 2 S 0 8 3 5 ...
Page 378: ... 377 6 F 2 S 0 8 3 5 Appendix R Failed Module Tracing and Replacement ...
Page 384: ... 383 6 F 2 S 0 8 3 5 Appendix S PLC Setting Sample ...
Page 386: ... 385 6 F 2 S 0 8 3 5 Appendix T Ordering ...
Page 392: ......