⎯
199
⎯
6
F
2
S
0
8
3
5
Iin
Iout
Iin = Iout
DIFI2
DIFI1 + 7/5 DIFI2
DIFI1
B
A
DIFI1, DIFI2: Setting value
screen.
•
Enter a signal number 270 for Term B to observe a signal PULSE at monitoring jack B, and
then press the ENTER key.
The phase of the test current is adjusted as follows.
•
Adjust the reference voltage to be in-phase with the pulse signal PULSE monitoring a CRT
oscilloscope.
•
Adjust the test current to be in-phase with the reference voltage to simulate an infeed current
and counter-phase to simulate an outflow current.
Figure 6.5.1.4 Phase Adjustment
Percentage restraint characteristics
The percentage restraint characteristic is tested on the outflow current (Iout) and infeed current
(Iin) plane as shown in Figure 6.5.1.5 by applying an infeed current to one relay and an outflow
current to another relay.
Figure 6.5.1.5 Percentage Restraining Characteristic on Iin-Iout Plane
Characteristic A is expressed by the following equation,
Iout
≤
(5/7) (Iin - DIFI1)
One cycle (20ms or 16.7ms)
PULSE
signal
Time
Reference
voltage
Testing
current
Summary of Contents for GRL100-101A
Page 223: ... 222 6 F 2 S 0 8 3 5 ...
Page 228: ... 227 6 F 2 S 0 8 3 5 Appendix B Signal List ...
Page 256: ... 255 6 F 2 S 0 8 3 5 Appendix C Variable Timer List ...
Page 258: ... 257 6 F 2 S 0 8 3 5 Appendix D Binary Output Default Setting List ...
Page 269: ... 268 6 F 2 S 0 8 3 5 ...
Page 270: ... 269 6 F 2 S 0 8 3 5 Appendix E Details of Relay Menu ...
Page 279: ... 278 6 F 2 S 0 8 3 5 ...
Page 288: ... 287 6 F 2 S 0 8 3 5 Appendix G Typical External Connection ...
Page 326: ... 325 6 F 2 S 0 8 3 5 Appendix J Return Repair Form ...
Page 330: ... 329 6 F 2 S 0 8 3 5 Customer Name Company Name Address Telephone No Facsimile No Signature ...
Page 331: ... 330 6 F 2 S 0 8 3 5 ...
Page 332: ... 331 6 F 2 S 0 8 3 5 Appendix K Technical Data ...
Page 343: ... 342 6 F 2 S 0 8 3 5 ...
Page 344: ... 343 6 F 2 S 0 8 3 5 Appendix L Symbols Used in Scheme Logic ...
Page 347: ... 346 6 F 2 S 0 8 3 5 ...
Page 348: ... 347 6 F 2 S 0 8 3 5 Appendix M Multi phase Autoreclose ...
Page 351: ... 350 6 F 2 S 0 8 3 5 ...
Page 352: ... 351 6 F 2 S 0 8 3 5 Appendix N Data Transmission Format ...
Page 358: ... 357 6 F 2 S 0 8 3 5 Appendix O Example of DIF and DIFG Setting ...
Page 364: ... 363 6 F 2 S 0 8 3 5 Appendix Q IEC60870 5 103 Interoperability ...
Page 377: ... 376 6 F 2 S 0 8 3 5 ...
Page 378: ... 377 6 F 2 S 0 8 3 5 Appendix R Failed Module Tracing and Replacement ...
Page 384: ... 383 6 F 2 S 0 8 3 5 Appendix S PLC Setting Sample ...
Page 386: ... 385 6 F 2 S 0 8 3 5 Appendix T Ordering ...
Page 392: ......