1-13
Themis Computer
Overview and Specifications
Chipset Overview
1.2.2
The Intel 6321 ESB I/O Controller Hub (ICH)
The Intel 6321 ESB I/O Controller Hub integrates an Ultra ATA 100 controller, six
Serial ATA host controller ports, one EHCI host controller, and four UHCI host con-
trollers supporting eight external USB 2.0 ports, LPC interface controller, flash
BIOS interface controller, PCI interface controller, Azalia / AC’97 digital controller,
integrated LAN controller, an ASF controller and a ESI for communication with the
MCH.
The Intel 6321 ESB I/O Controller Hub component provides the data buffering and
interface arbitration required to ensure that system interfaces operate efficiently and
provide the bandwidth necessary to enable the system to obtain peak performance.
The Intel 6321 ESB I/O Controller Hub elevates Serial ATA storage performance to
the next level with Intel
®
RAID.
The ACPI compliant Intel 6321 ESB I/O Controller Hub platform can support the
Full-on, Stop Grant, Suspend to RAM, Suspend to Disk, and Soft-Off power man-
agement states. Through the use of the integrated LAN functions, the Intel 6321 ESB
I/O Controller Hub also supports Alert Standard Format for remote management.
1.2.3
The Intel 6700 PCI-X 64-bit Hub (PXH-V)
The Intel 6700 PCI-X 64-bit hub (PXH-V) attaches directly to the MCH through a
point-to-point PCI-Express x8 or x4 link for support of PCI and PCI-X interfaces on
the platform. Each 6700PXH 64-bit PCI hub supports two bus segments that can be
independently configured to operate in PCI (33 MHz of 66 MHz) or PCI-X mode (at
66, 100, or 133 MHz) for 32-bit or 64-bit PCI/PCI-X devices.
Each PCI/PCI-X interface integrates a PCI standard hot-plug controller. The hub
supports multiple PCI-X slots and frequencies for the high-bandwidth I/O connectiv-
ity required for today’s server market.
1.2.4
Super I/O Controller
The Super I/O Controller chip disk-drive adapter functions include:
• a floppy disk drive controller (industry standard 82077/765 compatible)
• a data separator
• write pre-compensation circuitry
• decode logic
• data rate selection
Summary of Contents for RES-12DCX
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