Themis RES-12DCX, Installation Manual

Page: 40 / 144

1-12
Themis Computer
RES-12DCX Installation Manual
1.2 Chipset Overview
Built upon the functionality and the capability of the Intel 5000P (Blackford)
chipset, the RES-12DCX provides the performance and feature set required for dual
processor-based servers, including optimal configuration options for communica-
tions, presentation, storage, computation or database applications. The 5000P
chipset supports single or dual Xeon 64-bit dual-core and quad-core processors with
front-side bus speeds of up to 1.333 GHz. The Intel chipset consists of:
• the 5000P Memory Controller Hub (MCH)
• the Intel 6321 Enterprise South Bridge 2 (ESB2) I/O Controller Hub (ICH)
• the 6700 PCI-X 64-bit hub (PXH-V)
In addition, a Super I/O Controller chip offers a range of functions to increase the
I/O capability of the system.
1.2.1 The Intel 5000P Memory Controller Hub (MCH)
The 5000P Memory Controller Hub (MCH) chipset is designed for symmetric multi-
processing across two independent front side bus interfaces. Each front side bus uses
a 64-bit wide, 1.333 GHz data bus that transfers data at 10.7 GB/sec (for a total
bandwidth of 21.3 GB/sec.)
The MCH provides four channels of Fully-Buffered DIMM (FB-DIMM) memory.
Each of these channels can support up to four Dual Ranked FB-DIMM DDR2
DIMMs. FB-DIMM memory channels are organized in to two branches for support
of RAID 1 (mirroring). The RES-12DCX MCH chipset connects up to 8 fully-buff-
ered DIMM modules, providing a total of 32.0 GB/s for DDR2 667/533 FBD ECC
memory. The MCH chipset also provides three x4 PCI-Express interfaces to the
ESB2. In addition, the 5000P chipset offers a wide range of RAS features, including
memory interface ECC, x4/x8 Single Device Data Correction, CRC, parity protec-
tion, memory mirroring, and memory sparing.
The Xeon dual-core processor is designed to be used in conjunction with the chipset,
and provides the following features:
• L1 Cache Size: Instruction Cache (32KB/16KB), Data Cache (32KB/24KB)
• L2 Cache Size: 4MB (2MB per core)
• Data Bus Transfer Rate: 8.5 GB/s
• Package: FC-LGA6/FC-LGA4, 771 Lands