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Cr Buffer (1280
bytes)
Cb Buffer
(1280 bytes)
CRDST
CBDST
64
64
VDOUT[19−12]
8
8
Y Buffer
(2560 bytes)
YDSTA
64
VDOUT[9−2]
Display FIFO
8
1.3
Video Port Registers
Video Port Registers
For Y/C video display, the FIFO is configured as a single channel split into separate Y, Cb, and Cr buffers
with separate read pointers and write registers (YDSTA, CBDST, and CRDST).
shows how Y
data is output on the VDOUT[9-2] half of the bus and Cb/Cr data is multiplexed and output on the
VDOUT[19-12] half of the bus.
Figure 1-10. Y/C Video Display FIFO Configuration
The video port configuration register space is divided into several different sections with registers grouped
by function including top-level video port control, video capture control, video display control, and GPIO.
The registers for controlling the video port are in
The registers for controlling the video capture mode of operation are shown in
. An additional
space is dedicated for FIFO read pseudo-registers as shown in
. This space requires
high-speed access and is not mapped to the register access bus.
The registers for controlling the video display mode of operation are shown in
. An additional
space is dedicated for FIFO write pseudo-registers as shown in
. This space requires
high-speed access and is not mapped to the register access bus.
The registers for controlling the general-purpose input/output (GPIO) are shown in
SPRUEM1 – May 2007
Overview
25