www.ti.com
2.4.3 Video Port Interrupt Enable Register (VPIE)
Video Port Control Registers
The video port interrupt enable register (VPIE) enables sources of the video port interrupt to the DSP.
The video port interrupt enable register (VPIE) is shown in
and described in
Figure 2-3. Video Port Interrupt Enable Register (VPIE)
31
24
Reserved
R-0
23
22
21
20
19
18
17
16
LFDB
SFDB
VINTB2
VINTB1
SERRB
CCMPB
COVRB
GPIO
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
15
14
13
12
11
10
9
8
Reserved
DCNA
DCMP
DUND
TICK
STC
Reserved
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R-0
7
6
5
4
3
2
1
0
LFDA
SFDA
VINTA2
VINTA1
SERRA
CCMPA
COVRA
VIE
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 2-5. Video Port Interrupt Enable Register (VPIE) Field Descriptions
Bit
field
(1)
symval
(1)
Value
Description
31-24
Reserved
-
0
Reserved. The reserved bit location is always read as 0. A value written to this field
has no effect.
23
LFDB
OF(value)
Long field detected on channel B interrupt enable bit.
DEFAULT
0
Interrupt is disabled.
DISABLE
ENABLE
1
Interrupt is enabled.
22
SFDB
OF(value)
Short field detected on channel B interrupt enable bit.
DEFAULT
0
Interrupt is disabled.
DISABLE
ENABLE
1
Interrupt is enabled.
21
VINTB2
OF(value)
Channel B field 2 vertical interrupt enable bit.
DEFAULT
0
Interrupt is disabled.
DISABLE
ENABLE
1
Interrupt is enabled.
20
VINTB1
OF(value)
Channel B field 1 vertical interrupt enable bit.
DEFAULT
0
Interrupt is disabled.
DISABLE
ENABLE
1
Interrupt is enabled.
19
SERRB
OF(value)
Channel B synchronization error interrupt enable bit.
DEFAULT
0
Interrupt is disabled.
DISABLE
ENABLE
1
Interrupt is enabled.
18
CCMPB
OF(value)
Capture complete on channel B interrupt enable bit.
DEFAULT
0
Interrupt is disabled.
DISABLE
ENABLE
1
Interrupt is enabled.
(1)
For CSL implementation, use the notation VP_VPIE_field_symval
38
Video Port
SPRUEM1 – May 2007