3-39
TCI System Time Clock Compare Mask MSB Register (TCISTMSKM)
............................................
3-40
TCI System Time Clock Ticks Interrupt Register (TCITICKS)
........................................................
4-1
NTSC Compatible Interlaced Display
....................................................................................
4-2
SMPTE 296M Compatible Progressive Scan Display
.................................................................
4-3
Interlaced Blanking Intervals and Video Areas
.........................................................................
4-4
Progressive Blanking Intervals and Video Area
........................................................................
4-5
Horizontal Blanking and Horizontal Sync Timing
......................................................................
4-6
Vertical Blanking, Sync and Even/Odd Frame Signal Timing
........................................................
4-7
Video Display Module Synchronization Chain
..........................................................................
4-8
BT.656 Output Sequence
.................................................................................................
4-9
525/60 BT.656 Horizontal Blanking Timing
.............................................................................
4-10
625/50 BT.656 Horizontal Blanking Timing
.............................................................................
4-11
Digital Vertical F and V Transitions
.....................................................................................
4-12
8-Bit BT.656 FIFO Unpacking
...........................................................................................
4-13
Y/C Horizontal Blanking Timing (BT.1120 60I)
.......................................................................
4-14
8-Bit Y/C FIFO Unpacking
...............................................................................................
4-15
Chrominance Re-sampling
..............................................................................................
4-16
2x Co-Sited Scaling
4-17
2x Interspersed Scaling
..................................................................................................
4-18
Output Edge Pixel Replication
..........................................................................................
4-19
Luma Edge Replication
..................................................................................................
4-20
Interspersed Chroma Edge Replication
................................................................................
4-21
8-Bit Raw FIFO Unpacking
..............................................................................................
4-22
16-Bit Raw FIFO Unpacking
.............................................................................................
4-23
8-Bit Raw
FIFO Unpacking
...........................................................................................
4-24
Display Line Boundary Example
........................................................................................
4-25
BT.656 Interlaced Display Horizontal Timing Example
..............................................................
4-26
BT.656 Interlaced Display Vertical Timing Example
.................................................................
4-27
Raw Interlaced Display Horizontal Timing Example
.................................................................
4-28
Raw Interlaced Display Vertical Timing Example
.....................................................................
4-29
Y/C Progressive Display Horizontal Timing Example
................................................................
4-30
Y/C Progressive Display Vertical Timing Example
...................................................................
4-31
Video Display Status Register (VDSTAT)
.............................................................................
4-32
Video Display Control Register (VDCTL)
..............................................................................
4-33
Video Display Frame Size Register (VDFRMSZ)
.....................................................................
4-34
Video Display Horizontal Blanking Register (VDHBLNK)
...........................................................
4-35
Video Display Field 1 Vertical Blanking Start Register (VDVBLKS1)
..............................................
4-36
Video Display Field 1 Vertical Blanking End Register (VDVBLKE1)
...............................................
4-37
Video Display Field 2 Vertical Blanking Start Register (VDVBLKS2)
..............................................
4-38
Video Display Field 2 Vertical Blanking End Register (VDVBLKE2)
...............................................
4-39
Video Display Field 1 Image Offset Register (VDIMGOFF1)
.......................................................
4-40
Video Display Field 1 Image Size Register (VDIMGSZ1)
...........................................................
4-41
Video Display Field 2 Image Offset Register (VDIMGOFF2)
.......................................................
4-42
Video Display Field 2 Image Size Register (VDIMGSZ2)
...........................................................
4-43
Video Display Field 1 Timing Register (VDFLDT1)
..................................................................
4-44
Video Display Field 2 Timing Register (VDFLDT2)
..................................................................
4-45
Video Display Threshold Register (VDTHRLD)
.......................................................................
4-46
Video Display Horizontal Synchronization Register (VDHSYNC)
..................................................
4-47
Video Display Field 1 Vertical Synchronization Start Register (VDVSYNS1)
.....................................
4-48
Video Display Field 1 Vertical Synchronization End Register (VDVSYNE1)
.....................................
4-49
Video Display Field 2 Vertical Synchronization Start Register (VDVSYNS2)
.....................................
4-50
Video Display Field 2 Vertical Synchronization End Register (VDVSYNE2)
.....................................
4-51
Video Display Counter Reload Register (VDRELOAD)
..............................................................
SPRUEM1 – May 2007
List of Figures
9