www.ti.com
4.12 Video Display Registers
4.12.1 Video Display Status Register (VDSTAT)
Video Display Registers
The registers for controlling the video display mode of operation are listed in
. See the
device-specific datasheet for the memory address of these registers.
Table 4-5. Video Display Control Registers
Offset
Address
(1)
Acronym
Register Name
Section
200h
VDSTAT
Video Display Status Register
204h
VDCTL
Video Display Control Register
208h
VDFRMSZ
Video Display Frame Size Register
20Ch
VDHBLNK
Video Display Horizontal Blanking Register
210h
VDVBLKS1
Video Display Field 1 Vertical Blanking Start Register
214h
VDVBLKE1
Video Display Field 1 Vertical Blanking End Register
218h
VDVBLKS2
Video Display Field 2 Vertical Blanking Start Register
21Ch
VDVBLKE2
Video Display Field 2 Vertical Blanking End Register
220h
VDIMGOFF1
Video Display Field 1 Image Offset Register
224h
VDIMGSZ1
Video Display Field 1 Image Size Register
228h
VDIMGOFF2
Video Display Field 2 Image Offset Register
22Ch
VDIMGSZ2
Video Display Field 2 Image Size Register
230h
VDFLDT1
Video Display Field 1 Timing Register
234h
VDFLDT2
Video Display Field 2 Timing Register
238h
VDTHRLD
Video Display Threshold Register
23Ch
VDHSYNC
Video Display Horizontal Synchronization Register
240h
VDVSYNS1
Video Display Field 1 Vertical Synchronization Start Register
244h
VDVSYNE1
Video Display Field 1 Vertical Synchronization End Register
248h
VDVSYNS2
Video Display Field 2 Vertical Synchronization Start Register
24Ch
VDVSYNE2
Video Display Field 2 Vertical Synchronization End Register
250h
VDRELOAD
Video Display Counter Reload Register
254h
VDDISPEVT
Video Display Event Register
258h
VDCLIP
Video Display Clipping Register
25Ch
VDDEFVAL
Video Display Default Display Value Register
260h
VDVINT
Video Display Vertical Interrupt Register
264h
VDFBIT
Video Display Field Bit Register
268h
VDVBIT1
Video Display Field 1 Vertical Blanking Bit Register
26Ch
VDVBIT2
Video Display Field 2 Vertical Blanking Bit Register
(1)
The absolute address of the registers is device/port specific and is equal to the base a offset address. See the
device-specific datasheet to verify the register addresses.
The video display status register (VDSTAT) indicates the current display status of the video port.
The VDXPOS and VDYPOS bits track the coordinates of the most-recently displayed pixel. The F1D, F2D,
and FRMD bits indicate the completion of fields or frames and may need to be cleared by the DSP to
prevent a DCNA interrupt from being generated, depending on the selected frame operation. The F1D,
F2D, and FRMD bits are set when the final pixel from the appropriate field has been sent to the output
pad.
The video display status register (VDSTAT) is shown in
and described in
.
Video Display Port
122
SPRUEM1 – May 2007