6.3
Operational Details
..................................................................................................
6.4
Enabling VIC Port
....................................................................................................
6.5
VIC Port Registers
...................................................................................................
6.5.1
VIC Control Register (VICCTL)
..............................................................................
6.5.2
VIC Input Register (VICIN)
...................................................................................
6.5.3
VIC Clock Divider Register (VICDIV)
.......................................................................
SPRUEM1 – May 2007
Contents
7