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Texas Instruments TMS320DM647, User Manual

The Texas Instruments TMS320DM647 User Manual is a comprehensive guide designed to assist users in understanding and operating this cutting-edge product. Easily accessible for free download on our website, this manual provides detailed instructions, troubleshooting techniques, and essential information to optimize your experience with the TMS320DM647.

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4.12.3 Video Display Frame Size Register (VDFRMSZ)

4.12.4 Video Display Horizontal Blanking Register (VDHBLNK)

Video Display Registers

The video display frame size register (VDFRMSZ) sets the display channel frame size by setting the
ending values for the frame line counter (FLCOUNT) and the frame pixel counter (FPCOUNT).

The FPCOUNT starts at 0 and counts to FRMWIDTH - 1 before restarting. The FLCOUNT starts at 1 and
counts to FRMHEIGHT before restarting.

The video display frame size register (VDFRMSZ) is shown in

Figure 4-33

and described in

Table 4-8

.

Figure 4-33. Video Display Frame Size Register (VDFRMSZ)

31

28

27

16

Reserved

FRMHEIGHT

R-0

R/W-0

15

12

11

0

Reserved

FRMWIDTH

R-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 4-8. Video Display Frame Size Register (VDFRMSZ) Field Descriptions

Bit

field

(1)

symval

(1)

Value

Description

31-28

Reserved

-

0

Reserved. The reserved bit location is always read as 0. A value written to this field
has no effect.

27-16

FRMHEIGHT

OF(value)

0-FFFh

Defines the total number of lines per frame. The number is the ending value of the
frame line counter (FLCOUNT).
For BT.656 operation, the FRMHIGHT is set to 525 (525/60 operation) or 625
(625/50 operation).

DEFAULT

0

15-12

Reserved

-

0

Reserved. The reserved bit location is always read as 0. A value written to this field
has no effect.

11-0

FRMWIDTH

OF(value)

0-FFFh

Defines the total number of pixels per line including blanking. The number is the
frame pixel counter (FPCOUNT) ending value + 1.
For BT.656 operation, the FRMWIDTH is typically 858 or 864.

DEFAULT

0

(1)

For CSL implementation, use the notation VP_VDFRMSZ_field_symval

The video display horizontal blanking register (VDHBLNK) controls the display horizontal blanking.

Every time the frame pixel counter (FPCOUNT) is equal to HBLNKSTART, HBLNK is asserted.
HBLNKSTART also determines where the EAV code is inserted in the BT.656 and Y/C output.

Every time FPCOUNT = HBLNKSTOP, the HBLNK signal is de-asserted (this is shown in

Figure 4-5

). In

BT.656 and Y/C modes, HBLNKSTOP determines the SAV code insertion point and HBLNK de-assertion
point. The HBLNK inactive edge may optionally be delayed by 4 pixel clocks using the HBDLA bit.

The video display horizontal blanking register (VDHBLNK) is shown in

Figure 4-34

and described in

Table 4-9

SPRUEM1 – May 2007

Video Display Port

127

Submit Documentation Feedback

Summary of Contents for TMS320DM647

Page 1: ...TMS320DM647 DM648 Video Port VCXO Interpolated Control VIC Port User s Guide Literature Number SPRUEM1 May 2007 ...

Page 2: ...2 SPRUEM1 May 2007 Submit Documentation Feedback ...

Page 3: ...ration 32 2 3 1 Capture EDMA Event Generation 32 2 3 2 Display EDMA Event Generation 33 2 3 3 EDMA Size and Threshold Restrictions 33 2 3 4 EDMA Interface Operation 34 2 4 Video Port Control Registers 34 2 4 1 Video Port Control Register VPCTL 35 2 4 2 Video Port Status Register VPSTAT 37 2 4 3 Video Port Interrupt Enable Register VPIE 38 2 4 4 Video Port Interrupt Status Register VPIS 40 3 Video ...

Page 4: ...ideo in BT 656 or Y C Mode 67 3 10 1 Handling FIFO Overrun in BT 656 or Y C Mode 68 3 11 Capturing Video in Raw Data Mode 68 3 11 1 Handling FIFO Overrun Condition in Raw Data Mode 69 3 12 Capturing Data in TCI Capture Mode 69 3 12 1 Handling FIFO Overrun Condition in TCI Capture Mode 70 3 13 Video Capture Registers 70 3 13 1 Video Capture Channel x Status Register VCASTAT VCBSTAT 71 3 13 2 Video ...

Page 5: ...e 102 4 3 1 Y C Display Timing Reference Codes 102 4 3 2 Y C Blanking Codes 102 4 3 3 Y C Image Display 102 4 3 4 Y C FIFO Unpacking 103 4 4 Video Output Filtering 103 4 4 1 Output Filter Modes 103 4 4 2 Chrominance Re sampling Operation 104 4 4 3 Scaling Operation 104 4 4 4 Edge Pixel Replication 105 4 5 Ancillary Data Display 106 4 5 1 Horizontal Ancillary HANC Data Display 106 4 5 2 Vertical An...

Page 6: ... 20 Video Display Field 2 Vertical Synchronization End Register VDVSYNE2 140 4 12 21 Video Display Counter Reload Register VDRELOAD 141 4 12 22 Video Display Event Register VDDISPEVT 142 4 12 23 Video Display Clipping Register VDCLIP 142 4 12 24 Video Display Default Display Value Register VDDEFVAL 143 4 12 25 Video Display Vertical Interrupt Register VDVINT 144 4 12 26 Video Display Field Bit Reg...

Page 7: ... 6 4 Enabling VIC Port 170 6 5 VIC Port Registers 170 6 5 1 VIC Control Register VICCTL 171 6 5 2 VIC Input Register VICIN 172 6 5 3 VIC Clock Divider Register VICDIV 173 SPRUEM1 May 2007 Contents 7 Submit Documentation Feedback ...

Page 8: ... Bit Raw Data FIFO Packing 63 3 15 Parallel TCI Capture 64 3 16 Program Clock Reference PCR Header Format 64 3 17 System Time Clock Counter Operation 65 3 18 TCI FIFO Packing 66 3 19 TCI Timestamp Format Little Endian 66 3 20 Capture Line Boundary Example 67 3 21 Video Capture Channel x Status Register VCxSTAT 71 3 22 Video Capture Channel A Control Register VCACTL 73 3 23 Video Capture Channel x ...

Page 9: ...splay Vertical Timing Example 115 4 29 Y C Progressive Display Horizontal Timing Example 117 4 30 Y C Progressive Display Vertical Timing Example 118 4 31 Video Display Status Register VDSTAT 123 4 32 Video Display Control Register VDCTL 124 4 33 Video Display Frame Size Register VDFRMSZ 127 4 34 Video Display Horizontal Blanking Register VDHBLNK 128 4 35 Video Display Field 1 Vertical Blanking St...

Page 10: ...ter PCR 153 5 3 Video Port Pin Function Register PFUNC 154 5 4 Video Port Pin Direction Register PDIR 156 5 5 Video Port Pin Data Input Register PDIN 158 5 6 Video Port Pin Data Output Register PDOUT 159 5 7 Video Port Pin Data Set Register PDSET 161 5 8 Video Port Pin Data Clear Register PDCLR 162 5 9 Video Port Pin Interrupt Enable Register PIEN 163 5 10 Video Port Pin Interrupt Polarity Registe...

Page 11: ...s 77 3 18 Video Capture Channel x Field 2 Start Register VCxSTRT2 Field Descriptions 78 3 19 Video Capture Channel x Field 2 Stop Register VCxSTOP2 Field Descriptions 78 3 20 Video Capture Channel x Vertical Interrupt Register VCxVINT Field Descriptions 79 3 21 Video Capture Channel x Threshold Register VCxTHRLD Field Descriptions 80 3 22 Video Capture Channel x Event Count Register VCxEVTCT Field...

Page 12: ...egister VDRELOAD Field Descriptions 141 4 27 Video Display Event Register VDDISPEVT Field Descriptions 142 4 28 Video Display Clipping Register VDCLIP Field Descriptions 143 4 29 Video Display Default Display Value Register VDDEFVAL Field Descriptions 144 4 30 Video Display Vertical Interrupt Register VDVINT Field Descriptions 145 4 31 Video Display Field Bit Register VDFBIT Field Descriptions 146...

Page 13: ...U architecture pipeline instruction set and interrupts for the TMS320C64x and TMS320C64x digital signal processors DSPs of the TMS320C6000 DSP family The C64x C64x DSP generation comprises fixed point devices in the C6000 DSP platform The C64x DSP is an enhancement of the C64x DSP with added functionality and an expanded instruction set SPRUEK5 TMS320DM647 DM648 DSP DDR2 Memory Controller User s G...

Page 14: ...ce The PCI port interfaces to the DSP via the enhanced DMA EDMA controller This architecture allows for both PCI master and slave transactions while keeping the EDMA channel resources available for other applications SPRUEL5 TMS320DM647 DM648 DSP Host Port Interface UHPI User s Guide describes the host port interface HPI in the TMS320DM647 DM648 Digital Signal Processor DSP The HPI is a parallel p...

Page 15: ... the TMS320DM647 DM648 Digital Signal Processor DSP This reference guide provides the specifications for a 16 bit configurable synchronous serial peripheral interface The SPI is a programmable length shift register used for high speed communication between external peripherals or other DSPs Trademarks SPRUEM1 May 2007 Read This First 15 Submit Documentation Feedback ...

Page 16: ...SPs An overview of the video port functions FIFO configurations and signal mapping are included Topic Page 1 1 Video Port 17 1 2 Video Port FIFO 19 1 3 Video Port Registers 25 1 4 Video Port Pin Mapping 26 1 5 Video Port Pin Multiplexing 28 1 6 VideoPort Clocking 28 Overview 16 SPRUEM1 May 2007 Submit Documentation Feedback ...

Page 17: ...ideo SAV and end of active video EAV code insertion and horizontal and frame timing pulses Generates horizontal and vertical synchronization and blanking signals and a frame synchronization signal TCI capture mode Transport channel interface TCI from a front end device such as demodulator or a forward error correction device in 8 bit parallel format at up to 30 Mbytes sec The port generates up to ...

Page 18: ...eline Raw video capture pipeline VDIN 19 12 8 VDIN 19 2 16 DMA interface 64 Capture display buffer 2560 bytes 8 8 8 16 16 8 16 16 Timing and control logic VCTL2 VCTL3 VCLK1 VCTL1 VCLK2 DMA interface 8 8 64 32 VDOUT 19 12 8 VDOUT 19 2 16 BT 656 capture pipeline Video Port This document describes the full feature set offered by the video port See the device specific datasheet for details about I O t...

Page 19: ...ot adjust the transfer size based on buffer empty full status This means the EDMA transfer size is essentially fixed in the user programmed EDMA parameter table The preferred transfer size is often one entire line of data because this allows the most flexibility in terms of frame buffer line pitch in RAM Some modes of operation for the highest display rates may require more frequent EDMA requests ...

Page 20: ... has one of four configurations depending on the capture mode For BT 656 operation the FIFO is split into channel A and B as shown in Figure 1 2 Each FIFO is clocked independently with the channel A FIFO receiving data from the VDIN 9 2 half of the bus and the channel B FIFO receiving data from the VDIN 19 12 half of the bus Each channel s FIFO is further split into Y Cb and Cr buffers with separa...

Page 21: ...ndependently with the channel A FIFO receiving data from the VDIN 9 2 half of the bus and the channel B FIFO receiving data from the VDIN 19 12 half of the bus Each channel s FIFO has a separate write pointer and read register YSRCx The FIFO configuration is identical for TCI capture but channel B is disabled Figure 1 3 8 Bit Raw Video Capture and TCI Video Capture FIFO Configuration SPRUEM1 May 2...

Page 22: ...ngle channel split into separate Y Cb and Cr buffers with separate write pointers and read registers YSRCA CBSRCA and CRSRCA Figure 1 4 shows how Y data is received on the VDIN 9 2 half of the bus and Cb Cr data is received on the VDIN 19 12 half of the bus and de multiplexed into the Cb and Cr buffers Figure 1 4 Y C Video Capture FIFO Configuration 22 Overview SPRUEM1 May 2007 Submit Documentatio...

Page 23: ...e FIFO Configuration During video display operation the video port FIFO has one of five configurations depending on the display mode For BT 656 operation a single output is provided on channel A as shown in Figure 1 6 with data output on VDOUT 9 2 The channel s FIFO is split into Y Cb and Cr buffers with separate read pointers and write registers YDSTA CBDST and CRDST Figure 1 6 BT 656 Video Displ...

Page 24: ...gether and use the same clock and control signals Each channel uses a single buffer and write register YDSTx as shown in Figure 1 8 For 16 bit raw video the FIFO is configured as a single buffer as shown in Figure 1 9 The FIFO outputs data on VDOUT 19 2 The FIFO has a single read pointer and write register YDSTA Figure 1 8 8 Bit Locked Raw Video Display FIFO Configuration Figure 1 9 16 Bit Raw Vid...

Page 25: ...rs grouped by function including top level video port control video capture control video display control and GPIO The registers for controlling the video port are in Section 2 4 The registers for controlling the video capture mode of operation are shown in Section 3 13 An additional space is dedicated for FIFO read pseudo registers as shown in Section 3 14 This space requires high speed access an...

Page 26: ...n PACERR In In Ch A Ch A In 1 Legend VCLKINA Channel A capture clock CAPENA Channel A capture enable VCLKINB Channel B capture clock CAPENB Channel B capture enable AVID Active video HSYNC Horizontal synchronization VBLNK Vertical blanking VSYNC Vertical synchronization FID Field identification PACSTRT Packet start PACERR Packet error Table 1 2 Video Display Signal Mapping Usage Raw Data Display M...

Page 27: ...s 8 Bit 8 Bit 8 Bit 16 Bit TCI Mode VDIN19 B A C B A VDIN18 B A C B A VDIN17 B A C B A VDIN16 B A C B A VDIN15 B A C B A VDIN14 B A C B A VDIN13 B A C B A VDIN12 B A C B A VDIN9 A A Y A A A VDIN8 A A Y A A A VDIN7 A A Y A A A VDIN6 A A Y A A A VDIN5 A A Y A A A VDIN4 A A Y A A A VDIN3 A A Y A A A VDIN2 A A Y A A A 1 Legend A Channel A capture A C Channel A chroma A Y Channel A luma B Channel B cap...

Page 28: ...e Video Port have dedicated pins associated with them Each of the Video Port has its pins multiplexed with other peripherals In order to use a desired Video Port either in Capture or Display Mode the user would first need to program the Pin Mux Register PINMUX appropriately to ensure that the multiplexed pins work as VideoPort pins Refer to the device specific data manual to know details of the PI...

Page 29: ...s and types of resets interrupt operation EDMA operation external clock inputs video port throughput and latency and the video port control registers Topic Page 2 1 Reset Operation 30 2 2 Interrupt Operation 31 2 3 EDMA Operation 32 2 4 Video Port Control Registers 34 SPRUEM1 May 2007 Video Port 29 Submit Documentation Feedback ...

Page 30: ...CLK1 VCLK2 and STCLK are gated off to save peripheral power Peripheral bus accesses are acknowledged RREADY WREADY returned to prevent EDMA lock up Any value returned on reads data accepted or discarded on writes Peripheral bus MMR interface allows access to GPIO registers only PID PCR PFUNC PDIR PIN PDOUT PDSET PDCLR PIEN PIPOL PISTAT and PICLR Port I Os VD 19 2 VCTL1 VCTL2 VCTL3 and VCLK2 remain...

Page 31: ...When BLKCAP is cleared data capture and event generation may begin A software reset may be performed on the display channel by setting the RSTCH bit in VDCTL This reset requires that the channel VCLKIN be transitioning On display channel reset No new EDMA events are generated Peripheral bus accesses are acknowledged WREADY returned to prevent EDMA lock up Write data may be written into the FIFO or...

Page 32: ...rst read of the FIFO by the EDMA event service If the capture FIFO level exceeds 2x the VCTHRLDn value before the requested EDMA event completes then another EDMA event may be generated Thus up to one EDMA event may be outstanding An outgoing data counter counts data read by the EDMA This counter is loaded with the VCTHRLDn value whenever a new EDMA service begins The counter then counts down for ...

Page 33: ...because different lines are not packed together within a double word and the Cb and Cr thresholds 1 2 VCTHRLDx VDTHRLD are always rounded up to the double word For example in 8 bit BT 656 capture mode with a line length of 712 Y setting the threshold to the line length results in a VCTHRLD of 712 pixels x 1 bytes pixel x double word 8 bytes 89 double words The Cb and Cr FIFOs contain half the data...

Page 34: ...in the captured or displayed data and likely resulting in an eventual FIFO overflow or underflow In the same manner if another system EDMA incorrectly addresses the video port during active capture or display the video port has no way of determining that this is an errant EDMA because all it monitors is a EDMA access so it must perform the FIFO read or write Such an errant EDMA eventually causes t...

Page 35: ... port registers to their initial values VCLK1 and VCLK2 are configured as inputs and all VDATA and VCTL pins are placed in high impedance Auto cleared after reset is complete The VPRST bit may take several clock cycles to clear to 0 The VPRST bit should be polled to make sure the bit is cleared prior to writing to the video port registers 14 VPHLT OF value Video port halt bit This bit is set upon ...

Page 36: ...NE CAPTURE 1 TCI capture mode is enabled 1 DISP OF value Display mode select bit VDATA pins are configured for output VCLK2 pin is configured as VCLKOUT output DEFAULT 0 Capture mode is enabled CAPTURE DISPLAY 1 Display mode is enabled 0 DCHNL OF value Dual channel operation select bit If the DCDIS bit in VPSTAT is set this bit is forced to 0 DEFAULT 0 Single channel operation is enabled SINGLE DU...

Page 37: ...isable bit The default value is determined by the chip level configuration DEFAULT 0 Dual channel operation is enabled ENABLE DISABLE 1 Port muxing selections prevent dual channel operation 2 HIDATA OF value High data bus half HIDATA does not affect video port operation but is provided to inform you which VDATA pins may be controlled by the video port GPIO registers HIDATA is never set unless DCDI...

Page 38: ...ved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 23 LFDB OF value Long field detected on channel B interrupt enable bit DEFAULT 0 Interrupt is disabled DISABLE ENABLE 1 Interrupt is enabled 22 SFDB OF value Short field detected on channel B interrupt enable bit DEFAULT 0 Interrupt is disabled DISABLE ENABLE 1 Interrupt is enabled 21 VINTB2 OF...

Page 39: ...t DEFAULT 0 Interrupt is disabled DISABLE ENABLE 1 Interrupt is enabled 11 TICK OF value System time clock tick interrupt enable bit DEFAULT 0 Interrupt is disabled DISABLE ENABLE 1 Interrupt is enabled 10 STC OF value System time clock interrupt enable bit DEFAULT 0 Interrupt is disabled DISABLE ENABLE 1 Interrupt is enabled 9 8 Reserved 0 Reserved The reserved bit location is always read as 0 A ...

Page 40: ...errupt is only sent to the DSP if the corresponding enable bit in VPIE is set All VPIS bits are cleared by writing a 1 writing a 0 has no effect The video port interrupt status register VPIS is shown in Figure 2 4 and described in Table 2 6 Figure 2 4 Video Port Interrupt Status Register VPIS 31 24 Reserved R 0 23 22 21 20 19 18 17 16 LFDB SFDB VINTB2 VINTB1 SERRB CCMPB COVRB GPIO R WC 0 R WC 0 R ...

Page 41: ...cted NONE CLEAR 1 Interrupt is detected Bit is cleared 20 VINTB1 OF value Channel B field 1 vertical interrupt detected bit BT 656 or Y C capture mode VINTB1 is set when a vertical interrupt occurred in field 1 Raw data mode or TCI capture mode Not used DEFAULT 0 No interrupt is detected NONE CLEAR 1 Interrupt is detected Bit is cleared 19 SERRB OF value Channel B synchronization error interrupt d...

Page 42: ...been transferred from memory to the FIFO DCMP is set after displaying an entire field or frame when F1D F2D or FRMD in VDSTAT are set depending on the CON FRAME DF1 and DF2 control bits in VDCTL DEFAULT 0 No interrupt is detected NONE CLEAR 1 Interrupt is detected Bit is cleared 12 DUND OF value Display under run Indicates that the display FIFO ran out of data DEFAULT 0 No interrupt is detected NO...

Page 43: ... interrupt detected bit BT 656 or Y C capture mode or any display mode VINTA1 is set when a vertical interrupt occurred in field 1 Raw data mode or TCI capture mode Not used DEFAULT 0 No interrupt is detected NONE CLEAR 1 Interrupt is detected Bit is cleared 3 SERRA OF value Channel A synchronization error interrupt detected bit BT 656 or Y C capture mode Synchronization parity error on channel A ...

Page 44: ...overrun on channel A interrupt detected bit COVRA is set when data in the FIFO was overwritten before being read out by the EDMA DEFAULT 0 No interrupt is detected NONE CLEAR 1 Interrupt is detected Bit is cleared 0 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect Video Port 44 SPRUEM1 May 2007 Submit Documentation Feedback ...

Page 45: ...data to be captured within each field Frame and field synchronization can be performed using embedded sync codes or configurable control inputs allowing glueless interface to various encoders and ADCs Topic Page 3 1 Video Capture Mode Selection 46 3 2 BT 656 Video Capture Mode 46 3 3 Y C Video Capture Mode 50 3 4 BT 656 and Y C Mode Field and Frame Operation 51 3 5 Video Input Filtering 57 3 6 Anc...

Page 46: ... each component is written in packed form into separate FIFOs for transfer into Y Cb and Cr buffers in DSP memory This is commonly called planar format In BT 656 video capture mode data bytes in which the 8 bits are all set to 1 FFh or are all set to 0 00h are reserved for data identification purposes and consequently only 254 of the possible 256 8 bit words may be used to express signal value In ...

Page 47: ... 0 1 0 1 1 0 1 1 0 1 1 0 1 0 0 0 1 1 1 1 0 1 1 0 1 0 1 1 0 1 1 0 0 1 1 1 0 0 0 1 The protection bits allow the port to implement a DEDSEC double error detection single error correction function on the received video timing reference code The corrected values for the F H and V bits based on the protection bit values are shown in Table 3 4 The entries indicate detected double bit errors that cannot ...

Page 48: ...ition is defined by the VCxSTRT1 and VCxSTOP1 registers for field 1 and the VCxSTRT2 and VCxSTOP2 registers for field 2 The VCXSTART and VCXSTOP bits set the horizontal window position for the field relative to the HCOUNT pixel counter The VCYSTART and VCYSTOP bits set the vertical position relative to the VCOUNT line counter This is shown in Figure 3 1 HCOUNT increments on every chroma sample per...

Page 49: ...ords required to generate the events is set by the VCTHRLDn bits in VCxTHRLD On every YEVT the EDMA should move data from the Y buffer to DSP memory using the YSRC location as the source address On every CbEVT the EDMA should move data from the Cb buffer to DSP memory using the CBSRC location as the source address On every CrEVT the EDMA should move data from the Cr buffer to DSP memory using the ...

Page 50: ... EAV and SAV codes It also supports SDTV YCbCr modes that use separate control signals sometimes called CCIR601 mode As with the BT 656 capture mode data bytes where the 8 most significant bits are all set to 1 FFh or are all cleared to 0 00h are reserved for data identification purposes and consequentially only 254 of the possible 256 8 bit words may be used to express signal value Because Y C mo...

Page 51: ...ffers The video capture module uses the YEVT CbEVT and CrEVT events to notify the EDMA controller to copy data from the capture buffers to the DSP memory The number of pixels required to generate the events is set by the VCTHRLDn bits in VCxCTL the VCTHRLDn value must be an even number for Y C mode The capture module generates the events after VCTHRLD new pixels have been received On every YEVT th...

Page 52: ...ture operations as listed in Table 3 6 Table 3 6 BT 656 and Y C Mode Capture Operation VCxCTL Bit CON FRAME CF2 CF1 Operation 0 0 0 0 Reserved 0 0 0 1 Noncontinuous field 1 capture Capture only field 1 F1C is set after field 1 capture and causes CCMPx to be set The F1C bit must be cleared by the DSP before capture can continue The DSP has the entire field 2 time to clear F1C before next field 1 be...

Page 53: ... field the capture module must know which line should correspond to the first line of the field that is when to reset the line counter This point may vary depending on the type of capture being performed and the signals available for vertical synchronization The video port allows the vertical counter reset trigger to be determined by programming the EXC and VRST bits in VCxCTL The encoding of thes...

Page 54: ...Field FINV 0 FINV 1 Field 244 243 2 245 246 247 248 1 2 1 1 2 2 1 1 2 2 1 262 1 2 2 1 1 2 244 245 246 247 248 263 1 2 242 243 244 1 2 2 1 2 1 BT 656 and Y C Mode Field and Frame Operation VMode 2 and VMode 3 are used for BT 656 or Y C capture without embedded EAV SAV codes and allow alignment with either the active or inactive edge of the vertical control signal on VCTL2 This can be a VBLNK or VSY...

Page 55: ... 0 is used for BT 656 or Y C capture with embedded control and corresponds to the idea that each line begins with the horizontal blanking period It does not align with most standards that start counting with the first active pixel therefore is only useful if capturing of HANC data before the SAV code is desired HMode 1 is the default mode and corresponds to most digital video standards by making t...

Page 56: ...g VCxCTL Bit EXC FLDD Field Detect Method 0 0 EAV code 0 1 EAV code 1 0 Use FID input 1 1 Use field detect from HSYNC and VSYNC inputs In the BT 656 standard and in many Y C standards a field identification F bit is contained in EAV and SAV codes embedded in the data stream In the EAV field detect method the F bit in the EAV of the first line of every field is checked If F 0 then the current field...

Page 57: ...on is enabled by the SFDE and LFDE bits in VCxCTL The SFD and LFD bits in VPIS indicate when a short or long field occurred and trigger an interrupt to the DSP if enabled If a vertical blanking period is detected before the end of the capture field a short field is detected If EAV is used for vertical sync EXC 0 then a short field is detected when an EAV with V 1 occurs on or before VCOUNT VCYSTOP...

Page 58: ... filtering x10 x x No filtering x11 x x No filtering Chrominance re sampling computes chrominance values at sample points midway between the input luminance samples based on the input co sited chrominance samples This filter performs the horizontal portion of a conversion between YCbCr 4 2 2 format and YCbCr 4 2 0 format The vertical portion of the conversion must be performed in software The chro...

Page 59: ...the line are programmed using the VCXSTARTn and VCXSTOPn bits Note that when 1 2 scaling is selected horizontal timing applies to the incoming data before scaling The VCTHRLD value applies to the data written into the FIFO after scaling Also note when using the scalar standard BT 601 values should be used for the luma and chroma 16 240 data Using values beyond this range may result in overflow and...

Page 60: ...ows an example of a capture window that is smaller than the BT 656 active line Sample a is the first sample in the horizontal capture window and sample n is the last sample In this case any filtering done on the first sample location uses the m leading edge captured pixels m is 3 in this example and any filtering done on the last sample location uses the m trailing captured pixels From an implemen...

Page 61: ...If the SSE bit is set then when the VCEN bit is set to 1 the video port will not start capturing data until after detecting two vertical blanking intervals If the SSE bit is cleared to 0 capture begins immediately when the VCEN bit is set The incoming digital video capture data is stored in the FIFO which is 2560 bytes in dual channel operation or 5120 bytes deep in single channel operation The me...

Page 62: ...FRMC is set after data block capture and causes CCMPx to be set CCMPx interrupt can be disabled The port will continue capturing frames regardless of the state of FRMC 1 1 x x Reserved The CON bit controls the capture of multiple frames When CON 1 continuous capture is enabled the video port captures incoming frames assuming the VCEN bit is set without the need for DSP interaction It relies on a E...

Page 63: ...ng of data Eight bit parallel data is received on the input data bus Data is captured on the rising edge of VCLKIN The data consists typically of 188 byte packets with the first byte a SYNC byte also called a preamble The capture packet length is determined by the value of VCASTOP Data on the data bus is considered valid and captured only when the CAPEN signal is active TCI data capture begins wit...

Page 64: ... to synchronize to the system clock you should clock STCLK via the VPxCLK0 input Synchronization is an important aspect of decoding and presenting data in real time digital data delivery systems This is addressed in MPEG 2 transport packets by transmitting timing information in the adaptation fields of selected data packets This value serves as a reference for timing comparison in the receiving sy...

Page 65: ...to the DSP at any time through the system time clock registers TCISTCLKL and TCISTCLKM The DSP can program the video port to interrupt the DSP whenever a specific system time is reached or whenever a specific number of system time clock cycles have elapsed Since TCI mode captures only data packets there is no need for field control Some flexibility in capture and DSP notification is still provided...

Page 66: ...O The FIFO data packing is shown in Figure 3 18 Figure 3 18 TCI FIFO Packing The data capture circuitry signals to the synchronizing circuit when to take a timestamp of the hardware counters The FIFO write controller keeps track of the number of bytes received in a packet It multiplexes the timestamp data and the packet data onto the FIFO write data bus The timestamp and packet error information a...

Page 67: ...ition HCOUNT VCXSTOP occurs Thus every captured line begins on a double word boundary and non double word length lines are padded at the end An example is shown in Figure 3 20 In Figure 3 20 8 bit Y C mode the line length is not a double word When the condition HCOUNT VCXSTOP occurs the FIFO location is written even though 8 bytes have not been received The next capture line then begins in the nex...

Page 68: ...he F1C F2C or FRMC bits in VCxSTAT are set and cause the CCMPx bit in VPIS to be set This generates a DSP interrupt if the CCMPx bit is enabled in VPIE 13 If continuous capture is enabled the video port begins capturing again at the start of the next selected field or frame If noncontinuous field 1 and field 2 or frame capture is enabled the next field or frame is captured during which the DSP mus...

Page 69: ...gle frame capture is enabled capture is disabled until the DSP clears the FRMC bit at which point raw data sync must again be performed if enabled In case of a FIFO overrun the COVRx bit is set in VPIS This condition initiates an interrupt to the DSP if the overrun interrupt is enabled setting the COVRx bit in VPIE enables overrun interrupt The overrun interrupt routine should set the BLKCAP bit i...

Page 70: ...FIFO and blocks EDMA events for the channel As long as the BLKCAP bit is set the video capture channel ignores the incoming data but the internal data counter continues counting The BLKCAP bit should be cleared to 0 in order to continue capture Clearing the BLKCAP bit takes effect on the next PACSTRT EDMA events are still going to be blocked in the TCI packet in which the BLKCAP bit is cleared The...

Page 71: ...stem Time Clock Ticks Interrupt Register Section 3 13 20 The video capture channel x status register VCASTAT VCBSTAT indicates the current status of the video capture channel In BT 656 capture mode the VCXPOS and VCYPOS bits indicate the HCOUNT and VCOUNT values respectively to track the coordinates of the most recently received pixel The F1C F2C and FRMC bits indicate completion of fields or fram...

Page 72: ...eld 1 captured bit Write 1 to clear the bit a write of 0 has no effect DEFAULT 0 Field 1 has not been Not used Not used captured NONE CAPTURED 1 Field 1 has been Not used Not used captured CLEAR 27 16 VCYPOS OF value 0 FFFh Current VCOUNT Upper 12 bits of the data Upper 12 bits of the data value and the line that counter counter is currently being received within the current field DEFAULT 0 15 13 ...

Page 73: ...unctions as a capture FIFO reset without affecting the current programmable register values The F1C F2C and FRMC status bits in VCASTAT are not updated Field or frame complete interrupts and vertical interrupts are also not generated Clearing BLKCAP does not enable EDMA events during the field where the bit is cleared Whenever BLKCAP is set and then cleared the software needs to clear the field an...

Page 74: ... in VCACTL except RSTCH and BLKCAP bits may only be changed when VCEN 0 DEFAULT 0 Video capture is disabled DISABLE ENABLE 1 Video capture is enabled 14 13 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 12 LFDE OF value Long field detect enable bit DEFAULT 0 Long field detect is disabled Not used Not used DISABLE ENABLE 1 Long field de...

Page 75: ...6 6h Enables 16 bit raw mode Not used 2 For complete encoding of these bits see Table 3 6 Table 3 11 and Table 3 12 The captured image is a subset of the incoming image The video capture channel x field 1 start register VCASTRT1 VCBSTRT1 defines the start of the field 1 captured image Note that the size is defined relative to incoming data before scaling In BT 656 or Y C modes the horizontal pixel...

Page 76: ... written to this field has no effect 11 0 VCXSTART OF value 0 FFFh VCXSTART bits define the VCVBLNKP bits define Not used starting pixel number Must be the minimum CAPEN VCVBLNKP an even number LSB is inactive time to be treated as 0 interpreted as a vertical blanking period DEFAULT 0 1 For CSL implementation use the notation VP_VCxSTRT1_field_symval The video capture channel x field 1 stop regist...

Page 77: ...les samples DEFAULT 0 1 For CSL implementation use the notation VP_VCxSTOP1_field_symval The captured image is a subset of the incoming image The video capture channel x field 2 start register VCASTRT2 VCBSTRT2 defines the start of the field 2 captured image This allows different window alignment or size for each field Note that the size is defined relative to incoming data before scaling In BT 65...

Page 78: ...e their capture sizes are completely defined by the field 1 start and stop registers The video capture channel x field 2 stop register VCxSTOP2 is shown in Figure 3 26 and described in Table 3 19 Figure 3 26 Video Capture Channel x Field 2 Stop Register VCxSTOP2 31 28 27 16 Reserved VCYSTOP R 0 R W 0 15 12 11 0 Reserved VCXSTOP R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table ...

Page 79: ... Capture Channel x Vertical Interrupt Register VCxVINT Field Descriptions Description Bit field 1 symval 1 Value BT 656 or Y C Mode Raw Data Mode TCI Mode 31 VIF2 OF value Setting of VINT in field 2 enable bit DEFAULT 0 Setting of VINT in field 2 is Not used Not used disabled DISABLE ENABLE 1 Setting of VINT in field 2 is Not used Not used enabled 30 FSCL2 OF value FSYNC bit cleared in field 2 ena...

Page 80: ...s to be different from the field 1 EDMA size for some reason for example different captured line lengths in field 1 and field 2 If VT2EN is not set then the VCTHRLD1 value is used for both fields Note that the VCTHRLDn applies to data being written into the FIFO In the case of 8 bit BT 656 or Y C modes this means the output of any selected filter The video capture channel x threshold register VCxT...

Page 81: ... 11 0 Reserved CAPEVTCT1 R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 3 22 Video Capture Channel x Event Count Register VCxEVTCT Field Descriptions Description Bit field 1 symval 1 Value BT 656 or Y C Mode Raw Data Mode TCI Mode 31 28 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 27 16 CAPEVTCT2 OF value 0 FFF...

Page 82: ...ister values The F1C F2C and FRMC status bits in VCBSTAT are not updated Field or frame complete interrupts and vertical interrupts are also not generated Clearing BLKCAP does not enable EDMA events during the field where the bit is cleared Whenever BLKCAP is set and then cleared the software needs to clear the field and frame status bits F1C F2C and FRMC as part of the BLKCAP clear operation CLEA...

Page 83: ...BLE 1 Short field detect is enabled Not used Not used 10 RESMPL OF value Chroma re sampling enable bit DEFAULT 0 Chroma re sampling is disabled Not used Not used DISABLE ENABLE 1 Chroma is horizontally Not used Not used re sampled from 4 2 2 co sited to 4 2 0 interspersed before saving to chroma buffers 9 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this fie...

Page 84: ... and described in Table 3 24 Figure 3 31 TCI Capture Control Register TCICTL 31 16 Reserved R 0 15 6 5 4 3 2 1 0 Reserved ENSTC TCKEN STEN CTMODE ERRFILT Reserved R 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 3 24 TCI Capture Control Register TCICTL Field Descriptions Description Bit field 1 symval 1 Value BT 656 Y C Mode or Raw Data Mode TCI M...

Page 85: ...NITL is used to initialize the hardware counter to synchronize with the system time clock On receiving the first packet containing a program clock reference PCR and the PCR extension value the DSP writes the 32 least significant bits LSBs of the PCR into TCICLKINITL This initializes the counter to the system time clock TCICLKINITL should also be updated by the DSP whenever a discontinuity in the P...

Page 86: ... 31 16 Reserved R 0 15 10 9 1 0 Reserved INPCRE INPCRM R 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 3 26 TCI Clock Initialization MSB Register TCICLKINITM Field Descriptions Description BT 656 Y C Mode or Raw Data TCI Mode Bit field 1 symval 1 Value Mode 31 10 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effec...

Page 87: ...anges at a 27 MHz rate and is probably not reliably read by the DSP The PCRM bit normally changes at a 10 5 µHz rate every 26 hours The TCI system time clock MSB register TCISTCLKM is shown in Figure 3 35 and described in Table 3 28 Figure 3 35 TCI System Time Clock MSB Register TCISTCLKM 31 16 Reserved R 0 15 10 9 1 0 Reserved PCRE PCRM R 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value af...

Page 88: ...e LSB Register TCISTCMPL Field Descriptions Description Bit field symval 1 Value BT 656 Y C Mode or Raw Data Mode TCI Mode 31 0 ATC OF value 0 FFFF FFFFh Not used Contains the 32 LSBs of the absolute time compare DEFAULT 0 1 For CSL implementation use the notation VP_TCISTCMPL_ATC_symval The transport stream interface system time clock compare MSB register TCISTCMPM is used to generate an interrup...

Page 89: ...iting to TCISTMSKL The TCI system time clock compare mask LSB register TCISTMSKL is shown in Figure 3 38 and described in Table 3 31 Figure 3 38 TCI System Time Clock Compare Mask LSB Register TCISTMSKL 31 0 ATCM R W 0 LEGEND R W Read Write n value after reset Table 3 31 TCI System Time Clock Compare Mask LSB Register TCISTMSKL Field Descriptions Description Bit field symval 1 Value BT 656 Y C Mod...

Page 90: ... Note that the tick interrupt counter and comparison logic function are separate from the PCR logic and always count STCLK cycles regardless of the value of the CTMODE bit in TCICTL A write to TCITICKS resets the tick counter 0 Whenever the tick counter reaches the TICKCT value the TICK bit in VPIS is set and the counter resets to 0 To prevent inaccurate comparisons caused by changing register bit...

Page 91: ...fset address See the device specific datasheet to verify the register addresses Table 3 35 Video Capture FIFO Registers Function Capture Mode Register BT 656 or Y C Raw Data TCI YSRCx Maps Y capture buffer into DSP Maps data capture buffer into the Maps data capture buffer into the memory DSP memory DSP memory CBSRCx Maps Cb capture buffer into DSP Not used Not used memory CRSRCx Maps Cr capture b...

Page 92: ...play Mode 102 4 4 Video Output Filtering 103 4 5 Ancillary Data Display 106 4 6 Raw Data Display Mode 106 4 7 Video Display Field and Frame Operation 108 4 8 Display Line Boundary Conditions 109 4 9 Display Timing Examples 110 4 10 Displaying Video in BT 656 or Y C Mode 119 4 11 Displaying Video in Raw Data Mode 120 4 12 Video Display Registers 122 4 13 Video Display Registers Recommended Values 1...

Page 93: ... Cb Cr multiplexed channels 110 16 Bit Raw Display 16 bit data output Display devices generate interlaced images by controlling the vertical retrace timing The video display module emits a data stream used to generate a displayed image An NTSC compatible interlaced image with field and line information is shown in Figure 4 1 A progressive scan image SMPTE 296M compatible is shown in Figure 4 2 The...

Page 94: ...ne 30 Line 742 Line 744 Field 1 Line 27 Line 29 Line 745 Line 743 Line 741 Video Display Mode Selection Figure 4 2 SMPTE 296M Compatible Progressive Scan Display 94 Video Display Port SPRUEM1 May 2007 Submit Documentation Feedback ...

Page 95: ...ld 1 Active Video Field 1 Frame Field 2 Vertical Blanking Horizontal Blanking Field 2 Image Horiz Offset Field 2 Image Vertical Offset Field 2 Image Width Field 2 Image Height Field 2 Active Video Field 2 Video Display Mode Selection Figure 4 3 Interlaced Blanking Intervals and Video Areas SPRUEM1 May 2007 Video Display Port 95 Submit Documentation Feedback ...

Page 96: ...ge line counter ILCOUNT and the image pixel counter IPCOUNT track the visible image within the field ILCOUNT begins counting at the first display image line in each field IPCOUNT begins counting at the first displayed image pixel on each line They stop counting when they reach the image height and image width as specified in the video display field n image size register VDIMGSZn The video clock co...

Page 97: ...ntal synchronization signals are triggered HBLNK and HSYNC are shown active high Figure 4 5 Horizontal Blanking and Horizontal Sync Timing The 12 bit FLCOUNT counts which scan line is being generated The FLCOUNT is reset to 1 after reaching the count specified in VDFRMSZ For BT 656 operation the FRMHIGHT would be set to 525 525 60 operation or 625 625 50 operation The state of FLCOUNT is reflected...

Page 98: ...as an external horizontal sync input When the external HSYNC is asserted FPCOUNT is loaded with the HRLD value and VCCOUNT is loaded with the CRLD value VCTL2 may be configured as an external vertical sync input When the external VSYNC is asserted during field 1 FLCOUNT is loaded with the VRLD value Field determination is made using either VCTL3 as an external FLD input or by field detect logic us...

Page 99: ... is shown in Table 3 2 The EAV and SAV codes define the end and start of the horizontal blanking interval respectively and they also indicate the current field number and the vertical blanking interval The SAV and EAV codes have a 4 bit protection field to ensure valid codes The video display module generates these protection bits as part of the SAV and EAV codes Table 3 3 shows possible combinati...

Page 100: ...ge at EAV sequences The EAV and SAV sequences must occupy the first four words and the last four words of the digital horizontal blanking interval respectively The EAV code is inserted when FPCOUNT HBLNKSTART The SAV code is inserted when FPCOUNT HBLNKSTOP Table 4 2 BT 656 Frame Timing Line Number 625 50 525 60 F V Description 624 625 1 3 1 1 Vertical blanking for field 1 EAV SAV code still indica...

Page 101: ...location associated with it YDST CBDST and CRDST The pseudo registers are write only and are used by EDMAs to fill the FIFOs with output data The video display module multiplexes the data from the three FIFOs to generate the output CbYCrY data stream If video display is enabled the video display module uses the YEVT CbEVT and CrEVT events to notify the EDMA controller that data needs to be placed ...

Page 102: ...are used for data output the Y C output mode requires both halves of the video port data bus If the DCHDIS bit in VPCTL is set then Y C mode cannot be selected The EAV and SAV embedded timing codes are identical to those output in BT 656 mode and timing is controlled in the same manner In Y C mode however the codes must be output on both the Y and C data streams VDOUT 9 2 and VDOUT 19 12 An exampl...

Page 103: ...Os for color separation Samples are unpacked as shown in Figure 4 14 Figure 4 14 8 Bit Y C FIFO Unpacking The video output filter performs simple hardware scaling and re sampling on outgoing 8 bit BT 656 or 8 bit Y C data Filtering hardware is disabled during raw data display modes The output filter has four modes of operation no filtering 2x scaling chrominance re sampling and 2x scaling with chr...

Page 104: ...ling is shown in Figure 4 15 Figure 4 15 Chrominance Re sampling The 2x scaling mode is used to double the horizontal resolution of output luminance and chrominance data This allows processed CIF resolution images to be output at full size Vertical scaling must be performed in software Scaling for co sited source is shown in Figure 4 16 and scaling for interspersed source is shown in Figure 4 17 F...

Page 105: ...e Chroma Cb Cr samples a a b b c a y z z x x y a b c z x y Horizontal Image Size Leading edge replicated luma Trailing edge replicated luma z y Y a Ya Y b Yb Y c Yc Y x Yx Y y Yy Y z Yz Y a 1Ya 17Ya 17Yb 1Yc 32 Y b 1Ya 17Yb 17Yc 1Yd 32 Y z 1Yy 17Yz 17Yz 1Yy 32 Y y 1Yx 17Yy 17Yz 1Yz 32 Y x 1Yw 17Yx 17Yy 1Yz 32 Video Output Filtering Figure 4 17 2x Interspersed Scaling Because four tap filters are u...

Page 106: ...itional samples You must disable scaling and chroma re sampling when including the display of HANC data to prevent data corruption VANC or VBI data is commonly used for such features as teletext and closed captioning No special provisions are made for the display of VBI data VBI data may be displayed using the normal display mechanism by programming IMGVOFF to occur before the first line of active...

Page 107: ... samples INCPIX would be set to three in this case to indicate that a single pixel is represented by three output samples Sequential RGB samples output are also supported through a special FIFO unpacking mode When the 8 bit raw 3 4 unpacking is selected RGBX bit in VDCTL three output bytes are selected from each word and the fourth byte is ignored This allows the video port to correctly output dat...

Page 108: ...r than data from the display FIFO during the display image window The CON FRAME DF1 and DF2 bits encode the display operations as listed in Table 4 4 Table 4 4 Display Operation VDCTL Bit CON FRAME DF2 DF1 Operation 0 0 0 0 Reserved 0 0 0 1 Noncontinuous field 1 display Display only field 1 F1D is set after field 1 display and causes DCMPx to be set The F1D bit must be cleared by the DSP or a DCNA...

Page 109: ...el at which the FIFO has enough room to receive another EDMA block of data Depending on the size of the EDMA the FIFO may have room for multiple transfers before reaching the VDTHRLD level Once the threshold is reached another EDMA event is generated as soon as the FIFO again falls below the VDTHRLD level Once an entire field worth of data has been sent to the FIFO the video port may need to stop ...

Page 110: ...ut on external pins The actual delay can be longer or shorter as long as it is consistent within any display mode The BT 656 active line is 720 pixels wide Figure 4 25 shows the 704 pixel image window centered in the screen that results in an IMGHOFFx of 8 pixels The HBLNK and HSYNC signals are shown as they would be output for active low operation Note that only one of the two signals is actually...

Page 111: ... Y Def Cr Def Y Cb0 Y0 Cr0 Y1 Cb1 Y2 Cb351 Y702 Cr351 Y703 Def Cb Def Y Def Cb Def Y Def Cr Def Y FF C 00 0 00 0 XY 0 FRMWIDTH 858 IMGHOFF1 8 HSYNCSTART 736 HBLNKSTART 720 IMGHSIZE1 704 HSYNCSTOP 800 HBLNKSTOP 856 IMGHOFF2 8 IMGHSIZE2 704 Display Timing Examples Figure 4 25 BT 656 Interlaced Display Horizontal Timing Example A Assumes VCT0P bit in VPCTL is set to 1 active low output HSYNC output w...

Page 112: ... to 263 with VBLNKXSTART2 set to 360 while VBITSET2 is programmed to 264 For true BT 656 operation neither VBLNK nor VSYNC would be used The FLD output is setup to transition at the start of each analog field start of vertical blanking Since EAV F transitions on lines 4 and 266 this requires programming FBITCLR to 4 FBITSET to 266 FLD1YSTART to 1 and FLD2YSTART to 263 Note that FLD2XSTRT is 360 so...

Page 113: ...es Figure 4 26 BT 656 Interlaced Display Vertical Timing Example A Assumes VCT1P bit in VPCTL is set to 1 active low output VSYNC output when VCTL2S bit in VDCTL is set to 00 VBLNK output when VCTL2S bit is set 01 B If DVEN bit in VDCTL is set to 1 otherwise blanking value is output This section shows an example of raw display output for the same 704 x 408 interlaced image The horizontal output ti...

Page 114: ...ult Value Default Value Default Value Default Value Default Value Default Value Default Value Default Value Default Value Default Value Default Value Default Value Default Value Default Value Default Value Default Value Default Value Default Value Default Value Default Value Default Value FRMWIDTH 858 IMGHOFF1 8 HSYNCSTART 736 HBLNKSTART 720 IMGHSIZE1 704 HSYNCSTOP 800 HBLNKSTOP 0 IMGHOFF2 8 IMGHS...

Page 115: ...itor This example shows the more complex interlaced case The active field 1 is 242 5 lines high and active field 2 is 242 5 lines high This example shows the 480 line image window centered in the screen This results in an IMGVOFF1 of 2 lines and an IMGVOFF2 of 3 lines and also results in a non data half line at the end of field 1 and at the beginning of field 2 due to their non integer line length...

Page 116: ...as they would be output for active low operation Note that only one of the two signals is actually available externally The HBLNK inactive edge occurs either on sample 1646 coincident with the start of SAV or on sample 0 after SAV if the HBDLA bit is set For true SMPTE 296M operation neither HBLNK nor HSYNC would be used The IPCOUNT operation follows the description in Section 4 1 2 IPCOUNT resets...

Page 117: ...0 0 10 0 FF C 00 0 00 0 XY 0 FF C 00 0 00 0 XY 0 Def Cb Def Cr Def Cb Def Cr Def Y Def Y Def Y Def Y Def Cr Def Cb Def Y Def Y Cb0 Cr0 Y0 Y1 Y2 Y3 Y4 Y5 Cb1 Cr1 Cb2 Cr2 Y1260 Y1261 Y1262 Y1263 Def Y Def Y Def Y Def Y Def Y Def Y FF C 00 0 00 0 XY 0 FF C 00 0 00 0 XY 0 Cb630 Cr630 Cb631 Cr631 Def Cb Def Cr Def Cb Def Cr Def Cb Def Cr 00 0 FRMWIDTH 1650 IMGHOFF1 8 HSYNCSTART 1350 HBLNKSTART 1280 IMG...

Page 118: ... edges occur at the end of an active line so their XSTART XSTOP values are set to 1280 start of blanking The field 2 vertical timing start and stop registers are programmed to a value greater than 750 Since this value is never reached by FLCOUNT no extra VBLNK or VSYNC transitions occur For true SMPTE 296M operation neither VBLNK nor VSYNC would be used The FLD output is setup to transition low at...

Page 119: ...l where VBLNK goes inactive for field 2 10 Set VDIMGSZn Adjust the displayed image size by setting the HSIZE and VSIZE bits 11 Set VDIMOFF Adjust the displayed image offset within the active video area by setting HOFFSET and VOFFSET 12 Set the F bit timing in VDFBIT Specify the line where the F bit is cleared FBITCLR and the line where the F bit is set FBITSET 13 If external FLD output is required...

Page 120: ...blanking end for field 1 in VDVBLKE1 Specify the frame line VBLNKYSTOP1 and frame pixel counter VBLNKXSTOP1 values for the pixel where vertical blanking ends for field 1 8 Set VDIMGSZn Adjust the displayed image size by setting the HSIZE and VSIZE bits 9 Set VDIMOFF Adjust the displayed image offset within the active video area by setting HOFFSET and VOFFSET 10 Set the vertical blanking start for ...

Page 121: ...incorrect data may be output A FIFO under run occurs when the display FIFO is empty during an active display line because a pending EDMA request failed to load the data in time In case of a FIFO under run condition the DUND bit in VPIS is set This condition initiates an interrupt to the DSP if the under run interrupt is enabled the DUND bit in VPIE is set Because video display is typically a conti...

Page 122: ...play Field 1 Vertical Synchronization Start Register Section 4 12 17 244h VDVSYNE1 Video Display Field 1 Vertical Synchronization End Register Section 4 12 18 248h VDVSYNS2 Video Display Field 2 Vertical Synchronization Start Register Section 4 12 19 24Ch VDVSYNE2 Video Display Field 2 Vertical Synchronization End Register Section 4 12 20 250h VDRELOAD Video Display Counter Reload Register Section...

Page 123: ...been displayed NONE DISPLAYED 1 Field 1 has been displayed CLEAR 27 16 VDYPOS OF value 0 FFFh Current frame line counter FLCOUNT value Index of the current line in the current field being displayed by the module DEFAULT 0 15 14 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 13 VBLNK OF value Vertical blanking bit DEFAULT 0 Video displa...

Page 124: ...splay events bit BLKDIS functions as a display FIFO reset without affecting the current programmable register values The video display module continues to function normally the counters count control outputs are generated EAV SAV codes are generated for BT 656 and Y C modes and default or blanking data is output during active display time No data is moved to the display FIFOs because no events occ...

Page 125: ...output select bit DEFAULT 0 Output VSYNC VYSYNC VBLNK 1h Output VBLNK CSYNC 2h Output CSYNC FLD 3h Output FLD 17 16 VCTL1S OF value 0 3h VCTL1 output select bit DEFAULT 0 Output HSYNC HYSYNC HBLNK 1h Output HBLNK AVID 2h Output AVID FLD 3h Output FLD 15 VDEN OF value Video display enable bit Other bits in VDCTL except RSTCH and BLKDIS bits may only be changed when VDEN 0 DEFAULT 0 Video display is...

Page 126: ...ng select bit DEFAULT 0 No scaling Not used NONE X2 1 2 scaling Not used 7 CON 2 OF value Continuous display enable bit DEFAULT 0 Continuous display is disabled DISABLE ENABLE 1 Continuous display is enabled 6 FRAME 2 OF value Display frame bit DEFAULT 0 Do not display frame NONE FRMDIS 1 Display frame 5 DF2 2 OF value Display field 2 bit DEFAULT 0 Do not display field 2 NONE FLDDIS 1 Display fiel...

Page 127: ...ng value of the frame line counter FLCOUNT For BT 656 operation the FRMHIGHT is set to 525 525 60 operation or 625 625 50 operation DEFAULT 0 15 12 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 11 0 FRMWIDTH OF value 0 FFFh Defines the total number of pixels per line including blanking The number is the frame pixel counter FPCOUNT end...

Page 128: ...inactive edge is delayed by 4 Not used VCLKs 14 12 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 11 0 HBLNKSTART OF value 0 FFFh Location of EAV code and HBLNK Starting pixel FPCOUNT of blanking active edge within the line video area HBLNK active within the line DEFAULT 0 1 For CSL implementation use the notation VP_VDHBLNK_field_symv...

Page 129: ...pecifies the pixel in FPCOUNT Specifies the pixel in FPCOUNT where VBLNK active edge occurs for where vertical blanking begins VBLNK field 1 active edge for field 1 DEFAULT 0 1 For CSL implementation use the notation VP_VDVBLKS1_field_symval In raw data mode VBLNK is de asserted whenever the frame line counter FLCOUNT is equal to VBLNKYSTOP1 and the frame pixel counter FPCOUNT is equal to VBLNKXST...

Page 130: ...frame pixel counter FPCOUNT is equal to VBLNKXSTART2 this is shown in Figure 4 6 In BT 656 and Y C mode VBLNK is asserted whenever FLCOUNT VBLNKYSTART2 and FPCOUNT VBLNKXSTART2 This VBLNK output control is completely independent of the timing control codes The V bit in the EAV SAV codes for field 2 is controlled by the VDVBIT2 register The video display field 2 vertical blanking start register VDV...

Page 131: ...blanking end register VDVBLKE2 is shown in Figure 4 38 and described in Table 4 13 Figure 4 38 Video Display Field 2 Vertical Blanking End Register VDVBLKE2 31 28 27 16 Reserved VBLNKYSTOP2 R 0 R W 0 15 12 11 0 Reserved VBLNKXSTOP2 R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 4 13 Video Display Field 2 Vertical Blanking End Register VDVBLKE2 Field Descriptions Description ...

Page 132: ...isplay field 1 image offset register VDIMGOFF1 is shown in Figure 4 39 and described in Table 4 14 Figure 4 39 Video Display Field 1 Image Offset Register VDIMGOFF1 31 30 28 27 16 NV Reserved IMGVOFF1 R W 0 R 0 R W 0 15 14 12 11 0 NH Reserved IMGHOFF1 R W 0 R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 4 14 Video Display Field 1 Image Offset Register VDIMGOFF1 Field Descrip...

Page 133: ...nes Displayed image output stops when ILCOUNT IMGVSIZE1 The default output values or blanking values are output for the remainder of the active field The video display field 1 image size register VDIMGSZ1 is shown in Figure 4 40 and described in Table 4 15 Figure 4 40 Video Display Field 1 Image Size Register VDIMGSZ1 31 28 27 16 Reserved IMGVSIZE1 R 0 R W 0 15 12 11 0 Reserved IMGHSIZE1 R 0 R W 0...

Page 134: ...DIMGOFF2 31 30 28 27 16 NV Reserved IMGVOFF2 R W 0 R 0 R W 0 15 14 12 11 0 NH Reserved IMGHOFF2 R W 0 R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 4 16 Video Display Field 2 Image Offset Register VDIMGOFF2 Field Descriptions Description Bit field 1 symval 1 Value BT 656 and Y C Mode Raw Data Mode 31 NV OF value Negative vertical image offset enable bit DEFAULT 0 Not used N...

Page 135: ...tion Bit field 1 symval 1 Value BT 656 and Y C Mode Raw Data Mode 31 28 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 27 16 IMGVSIZE2 OF value 0 FFFh Specifies the display image height in lines DEFAULT 0 15 12 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 11 0 IMGHSIZE2 O...

Page 136: ...rame line counter FLCOUNT is equal to FLD2YSTART and the frame pixel counter FPCOUNT is equal to FLD2XSTART this is shown in Figure 4 6 In BT 656 and Y C mode the FLD signal is asserted to indicate field 2 display whenever FLCOUNT FLD2YSTART and FPCOUNT FLD2XSTART The FLD output is completely independent of the timing control codes The F bit in the EAV SAV codes is controlled by the VDFBIT registe...

Page 137: ...ts determine when the frame pixel counter FPCOUNT is incremented If for example each output value represents the R G or B portion of a display pixel then the INCPIX bits are set to 3h so that the pixel counter is incremented only on every third output clock An INCPIX value of 0h represents a count of 16 rather than 0 The video display threshold register VDTHRLD is shown in Figure 4 45 and describe...

Page 138: ...el counter FPCOUNT is equal to HSYNCSTART The HSYNC signal is de asserted to indicate the end of the horizontal sync pulse whenever FPCOUNT HSYNCSTOP Figure 4 46 Video Display Horizontal Synchronization Register VDHSYNC 31 28 27 16 Reserved HSYNCSTOP R 0 R W 0 15 12 11 0 Reserved HSYNCSTART R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 4 21 Video Display Horizontal Synchron...

Page 139: ...n field 1 DEFAULT 0 1 For CSL implementation use the notation VP_VDVSYNS1_field_symval The video display field 1 vertical synchronization end register VDVSYNE1 controls the end of vertical synchronization in field 1 The VDVSYNE1 is shown in Figure 4 48 and described in Table 4 23 Generation of the vertical synchronization is shown in Figure 4 6 The VSYNC signal is de asserted whenever the frame li...

Page 140: ...SYNCXSTART2 R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 4 24 Video Display Field 2 Vertical Synchronization Start Register VDVSYNS2 Field Descriptions Bit field 1 symval 1 Value Description 31 28 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 27 16 VSYNCYSTART2 OF value 0 FFFh Specifies the line where VSYNC is...

Page 141: ...horizontal or vertical synchronization are used the video display counter reload register VDRELOAD determines what values are loaded into the counters when an external sync is activated The video display counter reload register VDRELOAD is shown in Figure 4 51 and described in Table 4 26 Figure 4 51 Video Display Counter Reload Register VDRELOAD 31 28 27 16 Reserved VRLD R 0 R W 0 15 12 11 0 CRLD ...

Page 142: ...The reserved bit location is always read as 0 A value written to this field has no effect 11 0 DISPEVT1 OF value 0 FFFh Specifies the number of EDMA event Specifies the number of EDMA events sets YEVT CbEVT CrEVT to be YEVT to be generated for field 1 generated for field 1 output output DEFAULT 0 1 For CSL implementation use the notation VP_VDDISPEVT_DISPEVTn_symval The video display module in the...

Page 143: ... default value to be output during the portion of the active video window that is not part of the displayed image The default value is output during the non image display window portions of the active video This is the region between ILCOUNT 0 and ILCOUNT IMGVOFFn vertically and between IPCOUNT 0 and IPCOUNT IMGHOFFn horizontally In BT 656 mode CBDEFVAL YDEFVAL and CRDEFVAL are multiplexed on the ...

Page 144: ...effect 19 0 2 DEFVAL OF value 0 FFFFFh Not used Specifies the default raw data display value DEFAULT 0 23 16 CBDEFVAL OF value 0 FFh Specifies the 8 MSBs of the default Cb Not used display value DEFAULT 0 15 8 Reserved 0 Reserved The reserved bit location is Not used always read as 0 A value written to this field has no effect 7 0 YDEFVAL OF value 0 FFh Specifies the 8 MSBs of the default Y Not us...

Page 145: ...F value 0 FFFh Line where vertical interrupt VINT occurs if VIF1 bit is set DEFAULT 0 1 For CSL implementation use the notation VP_VDVINT_field_symval The video display field bit register VDFBIT controls the F bit value in the EAV and SAV timing control codes The FBITCLR and FBITSET bits control the F bit value in the EAV and SAV timing control codes The F bit is cleared to 0 indicating field 1 di...

Page 146: ...register VDVBIT1 controls the V bit value in the EAV and SAV timing control codes for field 1 The VBITSET1 and VBITCLR1 bits control the V bit value in the EAV and SAV timing control codes The V bit is set to 1 indicating the start of field 1 digital vertical blanking in the EAV code at the beginning of the line whenever the frame line counter FLCOUNT is equal to VBITSET1 It remains a 1 for all EA...

Page 147: ... of the line whenever the frame line counter FLCOUNT is equal to VBITSET2 It remains a 1 for all EAV SAV codes until the EAV at the beginning of the line on when FLCOUNT VBITCLR2 where it changes to 0 indicating the start of the field 2 digital active display The V bit operation is completely independent of the VBLNK control signal For correct interlaced operation the region defined by VBITSET2 an...

Page 148: ...RT 720 720 HBLNKSTOP 856 862 VDVBLKS1 VBLNKXSTART1 720 1 720 1 VBLNKYSTART1 1 1 624 1 VDVBLKE1 VBLNKXSTOP1 720 1 720 1 VBLNKYSTOP1 20 1 23 1 VDVBLKS2 VBLNKXSTART2 360 1 360 1 VBLNKYSTART2 263 1 311 1 VDVBLKE2 VBLNKXSTOP2 360 1 360 1 VBLNKYSTOP2 283 1 336 1 VDFLDT1 FLD1XSTART 720 1 720 1 FLD1YSTART 1 1 1 1 VDFLDT2 FLD2XSTART 360 1 360 1 FLD2YSTART 263 1 313 1 VDHSYNC HSYNCSTART 736 732 HSYNCSTOP 80...

Page 149: ...t specific and is equal to the FIFO base address offset address See the device specific datasheet to verify the register addresses Table 4 36 Video Display FIFO Registers Function Display Mode Register BT 656 or Y C Raw Data YDSTx Maps Y display FIFO into the DSP memory Maps data display buffer into the DSP memory CBDST Maps Cb display FIFO into the DSP memory Not used CRDST Maps Cr display FIFO i...

Page 150: ... O Operation Signals not used for video display or video capture can be used as general purpose input output GPIO signals Topic Page 5 1 GPIO Registers 151 General Purpose I O Operation 150 SPRUEM1 May 2007 Submit Documentation Feedback ...

Page 151: ...ster Section 5 1 5 28h PDIN Video Port Pin Data Input Register Section 5 1 6 2Ch PDOUT Video Port Pin Data Output Register Section 5 1 7 30h PDSET Video Port Pin Data Set Register Section 5 1 8 34h PDCLR Video Port Pin Data Clear Register Section 5 1 8 38h PIEN Video Port Pin Interrupt Enable Register Section 5 1 9 3Ch PIPOL Video Port Pin Interrupt Polarity Register Section 5 1 10 40h PISTAT Vide...

Page 152: ...ter reset A See the device specific datasheet for the default value of this field Table 5 2 Video Port Peripheral Identification Register VPPID Field Descriptions Bit field 1 symval 1 Value Description 31 24 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 23 16 TYPE OF value Identifies type of peripheral DEFAULT 01h Video port 15 8 CLAS...

Page 153: ... PCR 31 16 Reserved R 0 15 3 2 1 0 Reserved PEREN SOFT FREE R 0 R W 0 R 0 R W 1 LEGEND R W Read Write R Read only n value after reset Table 5 3 Video Port Peripheral Control Register PCR Field Descriptions Bit field 1 symval 1 Value Description 31 3 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 2 PEREN OF value Peripheral enable bit D...

Page 154: ...ved R 0 23 22 21 20 19 16 Reserved PFUNC22 PFUNC21 PFUNC20 Reserved R 0 R W 0 R W 0 R W 0 R W 0 15 11 10 9 8 Reserved PFUNC10 Reserved R 0 R W 0 R 0 7 1 0 Reserved PFUNC0 R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 5 4 Video Port Pin Function Register PFUNC Field Descriptions Bit field 1 symval 1 Value Description 31 23 Reserved 0 Reserved The reserved bit location is alw...

Page 155: ...EFAULT 0 Pins function normally NORMAL VDATA10TO19 1 Pins function as GPIO pin 9 1 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 0 PFUNC0 OF value PFUNC0 bit determines if VDATA 9 2 pins function as GPIO DEFAULT 0 Pins function normally NORMAL VDATA0TO9 1 Pins function as GPIO pin SPRUEM1 May 2007 General Purpose I O Operation 155 Sub...

Page 156: ... Value Description 31 23 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 22 PDIR22 OF value PDIR22 bit controls the direction of the VCTL3 pin DEFAULT 0 Pin functions as input VCTL3IN VCTL3OUT 1 Pin functions as output 21 PDIR21 OF value PDIR21 bit controls the direction of the VCTL2 pin DEFAULT 0 Pin functions as input VCTL2IN VCTL2OUT...

Page 157: ...AULT 0 Pins function as input VDATA8TO9IN VDATA8TO9OUT Pins function as output 7 5 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 4 PDIR4 OF value PDIR4 bit controls the direction of the VDATA 7 4 pins DEFAULT 0 Pins function as input VDATA4TO7IN VDATA4TO7OUT 1 Pins function as output 3 1 Reserved 0 Reserved The reserved bit location i...

Page 158: ...ND R W Read Write R Read only n value after reset Table 5 6 Video Port Pin Data Input Register PDIN Field Descriptions Bit field 1 symval 1 Value Description 31 23 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 22 PDIN22 OF value PDIN22 bit returns the logic level of the VCTL3 pin DEFAULT 0 Pin is logic low VCTL3LO VCTL3HI 1 Pin is log...

Page 159: ... 17 16 Reserved PDOUT22 PDOUT21 PDOUT20 PDOUT19 PDOUT18 PDOUT17 PDOUT16 R 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 15 14 13 12 11 10 9 8 PDOUT15 PDOUT14 PDOUT13 PDOUT12 Reserved Reserved PDOUT9 PDOUT8 W 0 W 0 W 0 W 0 R 0 R 0 W 0 W 0 7 6 5 4 3 2 1 0 PDOUT7 PDOUT6 PDOUT5 PDOUT4 PDOUT3 PDOUT2 Reserved Reserved W 0 W 0 W 0 W 0 W 0 W 0 R 0 R 0 LEGEND R W Read Write R Read only n value after reset Table 5 7 Video ...

Page 160: ...n input from pin When writing data writes to PDOUT20 bit DEFAULT 0 Pin drives low VCTL1LO VCTL1HI 1 Pin drives high 19 2 PDOUT 19 2 OF value PDOUT 19 2 bit drives the corresponding VDATA 19 2 pin only when the GPIO is configured as output When reading data returns the bit value in PDOUT n does not return input from pin When writing data writes to PDOUT n bit DEFAULT 0 Pin n drives low VDATAnLO VDA...

Page 161: ...ort Pin Data Set Register PDSET Field Descriptions Bit field 1 symval 1 Value Description 31 23 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 22 PDSET22 OF value Allows PDOUT22 bit to be set to a logic high without affecting other I O pins controlled by the same port DEFAULT 0 No effect NONE VCTL3HI 1 Sets PDOUT22 VCTL3 bit to 1 21 PD...

Page 162: ...ta Clear Register PDCLR Field Descriptions Bit field 1 symval 1 Value Description 31 23 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 22 PDCLR22 OF value Allows PDOUT22 bit to be cleared to a logic low without affecting other I O pins controlled by the same port DEFAULT 0 No effect NONE VCTL3CLR 1 Clears PDOUT22 VCTL3 bit to 0 21 PDCL...

Page 163: ...N5 PIEN4 PIEN3 PIEN2 Reserved Reserved W 0 W 0 W 0 W 0 W 0 W 0 R 0 R 0 LEGEND R W Read Write R Read only n value after reset Table 5 10 Video Port Pin Interrupt Enable Register PIEN Field Descriptions Bit field 1 symval 1 Value Description 31 23 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 22 PIEN22 OF value PIEN22 bit enables the in...

Page 164: ...22 OF value PIPOL22 bit determines the VCTL3 pin signal polarity that generates an interrupt DEFAULT 0 Interrupt is caused by a low to high transition on the VCTL3 pin VCTL3ACTHI VCTL3ACTLO 1 Interrupt is caused by a high to low transition on the VCTL3 pin 21 PIPOL21 OF value PIPOL21 bit determines the VCTL2 pin signal polarity that generates an interrupt DEFAULT 0 Interrupt is caused by a low to ...

Page 165: ...erved PISTAT9 PISTAT8 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 7 6 5 4 3 2 1 0 PISTAT7 PISTAT6 PISTAT5 PISTAT4 PISTAT3 PISTAT2 Reserved Reserved R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 LEGEND R W Read Write R Read only n value after reset Table 5 12 Video Port Pin Interrupt Status Register PISTAT Field Descriptions Bit field 1 symval 1 Value Description 31 23 Reserved 0 Reserved The reserved bit location is always...

Page 166: ... W 0 W 0 R 0 R 0 LEGEND R W Read Write R Read only n value after reset Table 5 13 Video Port Pin Interrupt Clear Register PICLR Field Descriptions Bit field 1 symval 1 Value Description 31 23 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 22 PICLR22 OF value Allows PISTAT22 bit to be cleared to a logic low DEFAULT 0 No effect NONE VCTL...

Page 167: ...ides an overview of the VCXO interpolated control VIC port Topic Page 6 1 Overview 168 6 2 Interface 168 6 3 Operational Details 169 6 4 Enabling VIC Port 170 6 5 VIC Port Registers 170 SPRUEM1 May 2007 VCXO Interpolated Control Port 167 Submit Documentation Feedback ...

Page 168: ...n the resolution needed When the video port is used in transport stream interface TCI mode the VIC port is used to control the system clock VCXO for MPEG transport stream Figure 6 1 The VIC port supports following features Single bit interpolated VCXO control Programmable precision from 9 to 16 bits Figure 6 1 TCI System Block Diagram The pin list for VIC port is shown in Table 6 1 pins are 3 3V I...

Page 169: ...ock STCLK input driven by an external VCXO controlled by the VIC port On reception of a packet the video port captures a snapshot of the counter Software uses this timestamp to determine the deviation of the system time clock from the server clock and drives VCTL output of the VIC port to keep it synchronized Any time a packet with a PCR is received the timestamp for that packet is compared with t...

Page 170: ...code is available for interpolation Repeat step Step 1 as often as needed The VIC port registers are listed in Table 6 3 See the device specific datasheet for the memory address of these registers Table 6 3 VIC Port Registers Offset Address 1 Acronym Register Name Section 00h VICCTL VIC Control Register Section 6 5 1 04h VICIN VIC Input Register Section 6 5 2 08h VICDIV VIC Clock Divider Register ...

Page 171: ...s 10BITS 6h 10 bits 9BITS 7h 9 bits 0 GO OF value The GO bit can be written to at any time DEFAULT 0 The VICDIV and VICCTL registers can be written to without affecting the operation of the VIC port All the logic in the VIC port is held in reset state and a 0 is output on the 0 VCTL output line A write to VICCTL bits as well as setting GO to 1 is allowed in a single write operation The VICCTL bits...

Page 172: ...ed in Table 6 5 Figure 6 4 VIC Input Register VICIN 31 16 Reserved R 0 15 0 VICINBITS R W 0 LEGEND R W Read Write R Read only n value after reset Table 6 5 VIC Input Register VICIN Field Descriptions Bit field symval 1 Value Description 31 16 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 15 0 VICINBITS OF value 0 FFFFh The DSP writes ...

Page 173: ...VICCTL is cleared to 0 If a write is performed when the GO bit is set to 1 the VICDIV bits remain unchanged The VIC clock divider register VICDIV is shown in Figure 6 5 and described in Table 6 6 Figure 6 5 VIC Clock Divider Register VICDIV 31 16 Reserved R 0 15 0 VICCLKDIV R W 0001h LEGEND R W Read Write R Read only n value after reset Table 6 6 VIC Clock Divider Register VICDIV Field Description...

Page 174: ...siness practice TI is not responsible or liable for any such statements TI products are not authorized for use in safety critical applications such as life support where a failure of the TI product would reasonably be expected to cause severe personal injury or death unless officers of the parties have executed an agreement specifically governing such use Buyers represent that they have all necess...

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