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5.1.4 Video Port Pin Direction Register (PDIR)
GPIO Registers
The PDIR controls the direction of IO pins in the video port for those pins set by PFUNC. If a bit is set to
1, the relevant pin or pin group acts as an output. If a bit is cleared to 0, the pin or pin group functions as
an input. The PDIR settings do not affect pins where the corresponding PFUNC bit is not set.
The video port pin direction register (PDIR) is shown in
and described in
Figure 5-4. Video Port Pin Direction Register (PDIR)
31
24
Reserved
R-0
23
22
21
20
19
17
16
Reserved
PDIR22
PDIR21
PDIR20
Reserved
PDIR16
R-0
R/W-0
R/W-0
R/W-0
R-0
R/W-0
15
13
12
11
9
8
Reserved
PDIR12
Reserved
PDIR8
R-0
R/W-0
R-0
R/W-0
7
5
4
3
1
0
Reserved
PDIR4
Reserved
PDIR0
R-0
R/W-0
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-5. Video Port Pin Direction Register (PDIR) Field Descriptions
Bit
field
(1)
symval
(1)
Value Description
31-23
Reserved
-
0
Reserved. The reserved bit location is always read as 0. A value written to this
field has no effect.
22
PDIR22
OF(value)
PDIR22 bit controls the direction of the VCTL3 pin.
DEFAULT
0
Pin functions as input.
VCTL3IN
VCTL3OUT
1
Pin functions as output.
21
PDIR21
OF(value)
PDIR21 bit controls the direction of the VCTL2 pin.
DEFAULT
0
Pin functions as input.
VCTL2IN
VCTL2OUT
1
Pin functions as output.
20
PDIR20
OF(value)
PDIR20 bit controls the direction of the VCTL1 pin.
DEFAULT
0
Pin functions as input.
VCTL1IN
VCTL1OUT
1
Pin functions as output.
19-17
Reserved
-
0
Reserved. The reserved bit location is always read as 0. A value written to this
field has no effect.
16
PDIR16
OF(value)
PDIR16 bit controls the direction of the VDATA[19-16] pins.
DEFAULT
0
Pins function as input.
VDATA16TO19IN
VDATA16TO19OUT
1
Pins function as output.
15-13
Reserved
-
0
Reserved. The reserved bit location is always read as 0. A value written to this
field has no effect.
(1)
For CSL implementation, use the notation VP_PDIR_field_symval
156
General-Purpose I/O Operation
SPRUEM1 – May 2007