ADV
ANCEINFORMA
TION
TMS320F28377S, TMS320F28376S, TMS320F28375S, TMS320F28374S
SPRS881A – AUGUST 2014 – REVISED JUNE 2015
TMS320F2837xS Delfino™ Microcontrollers
1
Device Overview
1.1
Features
1
• TMS320C28x 32-Bit CPU
• Analog Subsystem
– 200 MHz
– Up to Four Dual-Mode Analog-to-Digital
Converters (ADCs)
– IEEE 754 Single-Precision Floating-Point
•
16-Bit Mode
– Trigonometric Math Unit (TMU)
–
1.1 MSPS Each (up to 4.4-MSPS
– Viterbi/Complex Math Unit (VCU-II)
System)
• Programmable Control Law Accelerator (CLA)
–
Differential
– 200 MHz
–
Up to 12 External Channels
– IEEE 754 Single-Precision Floating-Point
•
12-Bit Mode
Executes Code Independently of Main CPU
–
3.5 MSPS Each (up to 14-MSPS System)
• On-Chip Memory
–
Single-Ended
– 512KB or 1MB of Flash (ECC-Protected)
–
Up to 24 External Channels
– 132KB or 164KB of RAM (ECC or Parity)
•
Single Sample-and-Hold (S/H) on Each ADC
– Dual-Zone Security Supporting Third-Party
Development
•
HW Integrated Post-Processing of ADC
Conversions
• Clock and System Control
–
Saturating Offset Calibration
– Two Internal Zero-Pin 10-MHz Oscillators
–
Error From Setpoint Calculation
– On-Chip Crystal Oscillator and External Clock
Input
–
High, Low, and Zero-Crossing Compare,
With Interrupt Capability
– Windowed Watchdog Timer Module
–
Trigger-to-Sample Delay Capture
– Missing Clock Detection Circuitry
– Eight Windowed Comparators With 12-Bit
• 1.2-V Core, 3.3-V I/O Design
Digital-to-Analog Converter (DAC) References
• System Peripherals
– Three 12-Bit Buffered DAC Outputs
– Two External Memory Interfaces (EMIFs) With
• Enhanced Control Peripherals
ASRAM and SDRAM Support
– Up to 24 PWM Channels With Enhanced
– 6-Channel Direct Memory Access (DMA)
Features
Controller
– Up to 16 High-Resolution Pulse Width
– Up to 169 Individually Programmable,
Modulator (HRPWM) Channels
Multiplexed General-Purpose Input/Output
(GPIO) Pins With Input Filtering
•
High Resolution on Both A and B Channels
of 8 PWM Modules
– Hardware (HW) Interrupt Controller
•
Dead-Band Support (on Both Standard and
– Multiple Low-Power Mode Support With External
High Resolution)
Wakeup
– Six Enhanced Capture (eCAP) Modules
– JTAG Emulation Connection
– Up to Three Enhanced Quadrature Encoder
• Communications Peripherals
Pulse (eQEP) Modules
– USB 2.0 (MAC + PHY)
– Eight Sigma-Delta Filter Module (SDFM) Input
– Support for 12-Pin 3.3 V-Compatible Universal
Channels, 2 Parallel Filters per Channel
Parallel Port (uPP) Interface
•
Standard SDFM Data Filtering
– Two Controller Area Network, D_CAN, Modules
(Pin-Bootable)
•
Comparator Filter for Fast Action for Out of
Range
– Three High-Speed (40-MHz) SPI Ports
(Pin-Bootable)
– Two Multichannel Buffered Serial Ports
(McBSPs)
– Up to Four Serial Communications Interfaces
(SCIs) (Pin-Bootable)
– Two I
2
C Interfaces (Pin-Bootable)
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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. ADVANCE INFORMATION for pre-production products; subject to
change without notice.
