Terasic Apollo S10, User Manual

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Apoolo-S10
User Manual 78 www.terasic.com
March 31, 2020
Figure 3-6 System Configuration Group

Programmable Clock Generator
There are two external clock generator Si5340A on-board that provide reference clocks
for the following signals:

DDR4B_REFCLK

FMC_REFCLK0

FMC_REFCLK1

FMCP_REFCLK0

FMCP_REFCLK1

FMCP_REFCLK2

DDR4C_REFCLK

LVDS_REFCLK
To use these clock, users can select the desired frequency on the Si5340A, as shown
in Figure 3-7 . DDR4 or FMC/FMC+ must be checked before users can start to specify
the desired frequency in the programmable oscillators.