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Apoolo-S10
User Manual

62

www.terasic.com

March 31, 2020

DDR4A_A17

Address [17]/ NC

SSTL-12

PIN_L35

DDR4A_BA0

Bank Select [0]

SSTL-12

PIN_L36

DDR4A_BA1

Bank Select [1]

SSTL-12

PIN_T35

DDR4A_BG0

Bank Group Select

[0]

SSTL-12

PIN_R36

DDR4A_BG1

Bank Group Select

[1]

SSTL-12

PIN_D40

DDR4A_CK

Clock p

DIFFERENTIAL 1.2-V

SSTL

PIN_F39

DDR4A_CK_n

Clock n

DIFFERENTIAL 1.2-V

SSTL

PIN_G39

DDR4A_CKE0

Clock Enable pin

SSTL-12

PIN_L40

DDR4A_CKE1

Clock Enable pin

SSTL-12

PIN_K40

DDR4A_ODT0

On Die

Termination

SSTL-12

PIN_G40

DDR4A_ODT1

On Die

Termination

SSTL-12

PIN_F40

DDR4A_CS_n0

Chip Select

SSTL-12

PIN_G38

DDR4A_CS_n1

Chip Select

SSTL-12

PIN_J40

DDR4A_PAR

Command and

Address Parity

Input

SSTL-12

PIN_H40

DDR4A_ALERT_n

Register ALERT_n

output

1.2 V

PIN_A38

DDR4A_ACT_n

Activation

Command Input

SSTL-12

PIN_H38

DDR4A_RESET_n

Chip Reset

1.2 V

PIN_E40

DDR4A_REFCLK_p

DDR4 A port

Reference Clock p

LVDS

PIN_M35

DDR4A_REFCLK_n

DDR4 A port

Reference Clock n

LVDS

PIN_N35

DDR4A_RZQ

External precision

resistor

1.2 V

PIN_P34

Table 2-23 DDR4B Pin Assignments, Schematic Signal Names, and Functions

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Summary of Contents for Apollo S10

Page 1: ...Apoolo S10 User Manual 1 www terasic com March 31 2020 1 1 Q...

Page 2: ...tures 6 1 3 Block Diagram 8 1 4 Mechanical Specifications 8 1 5 Power Requirement 10 1 6 Connectivity 11 Chapter 2 Board Component 14 2 1 Configuration Interface 14 2 2 Setup and Status Components 18...

Page 3: ...Ethernet 69 2 12 1x6 GPIO Header 70 2 13 System Status Interface 71 Chapter 3 System Builder 73 3 1 Introduction 73 3 2 General Design Flow 74 3 3 Using System Builder 75 Chapter 4 Dashboard GUI 84 4...

Page 4: ...elements to obtain speed and power breakthrough with up to 70 lower power Combining a number of high end hardware interfaces such as high capacity and high bandwidth DDR4 SDRAM up to 32GB on board USB...

Page 5: ...Apoolo S10 User Manual 5 www terasic com March 31 2020 Figure 1 1 Apollo S10 board top...

Page 6: ...1 3 Key Features The following hardware is implemented on the Apollo S10 board FPGA Device Intel Stratix 10 SoC FPGA 1SX280HU2F50 2 800K logic elements LEs 229 Mbits embedded memory M20K 96 transceiv...

Page 7: ...8V 1 5V 1 2V Selection FMC Vita57 4 connector with 24 transceivers FMC VADJ 1 8V 1 5V 1 2V Selection Two 50Mhz Single ended Clock Source Clock Generator Si5341 LED x2 Button x2 Dip Switch x2 CPU Rese...

Page 8: ...Apollo S10 board To provide maximum flexibility for the users all key components are connected to the Stratix 10 SX FPGA device Thus users can configure the FPGA to implement any system design Figure...

Page 9: ...Apoolo S10 User Manual 9 www terasic com March 31 2020 Figure 1 4 Top side mechanical layout Figure 1 5 Bottom side mechanical layout...

Page 10: ...er Connector Connect to the based board If user wants use the Apollo S10 board as the module board and connect it to the carrier board The carrier board needs to provide at least 12V 15A power to the...

Page 11: ...connector for connecting based board 1 6 Connectivity The Apollo S10 board provides FMC and FMC connector as expansion interface Users can use Apollo S10 as stand alone connect FMC daughter card See...

Page 12: ...ectors are needed to be used they are FMC FMC and Power connector See Figure 1 10 The following table lists the manufacturer and manufacturer part numbers of the three connectors that can match with t...

Page 13: ...Apoolo S10 User Manual 13 www terasic com March 31 2020 Figure 1 10 Part Number of the connector for based board...

Page 14: ...igure 2 1 the mode select pin of the FPGA on the Apollo S10 board has been set to Active Serial AS mode using resistors Thus the Apollo S10 board supports the following configuration modes JTAG Mode C...

Page 15: ...ode process and interface The SDM will load the initial configuration firmware from the QSPI flash to configure the FPGA including FPGA I O and core configuration HPS part of the boot can also be comp...

Page 16: ...e The factory setting of the SoC boot of the Apollo S10 board is the FPGA Configuration First Mode The architecture is shown in the Figure 2 3 Two storage mediums are used The system needs QSPI flash...

Page 17: ...s the HPS reset to let the HPS start using the FSBL hardware handoff file to setup the clocks HPS dedicated I Os and peripherals The FSBL then loads the SSBL Second Stage Boot Loader from the Micro SD...

Page 18: ...tch 0 03 for Linux run Download the version 19 1 patch 0 03 for Window run Download the Readme for the version 19 1 patch 0 03 txt 2 2 Setup and Status Components This section will introduce the use o...

Page 19: ...s or the power consumption exceeds 180W all the power of the FPGA will be cut off and the D9 will be flashing JTAG Interface Switch The JTAG interface switch SW4 is to set whether the JTAG interface o...

Page 20: ...e the JTAG interface of the FMC connector into the JTAG chain ON FMC_VCCIO and FMCP_VCCIO Select Header The FMC and FMC connector I O standard on the Apollo S10 can be set to three voltages 1 8V 1 5V...

Page 21: ...erasic com March 31 2020 Table 2 3 JP2 Setting for FMC I O standard JP2 Setting FMC I O Standard 1 2V 1 5V 1 8V Default Setting Table 2 4 JP3 Setting for FMC I O standard JP3 Setting FMC I O Standard...

Page 22: ...e 2 6 list the information of the push button for the HPS fabric Table 2 5 Push button FPGA fabric Pin Assignments Schematic Signal Names and Functions Board Reference Schematic Signal Name Descriptio...

Page 23: ...vice Each LED is driven directly by the Stratix 10 SX FPGA The LED is turned on or off when the associated pins are driven to a low or high logic level respectively A list of the pin names on the FPGA...

Page 24: ...ween the HPS and Micro SD card socket Table 2 10 lists the pin assignment of Micro SD card socket to the HPS Figure 2 6 Pin out of Micro SD Card socket Table 2 10 Micro SD Card Socket Header Pin Assig...

Page 25: ...rs and single ended or differential signaling There is one FMC connector on the Apollo S10 board it is a High Pin Count HPC size of connector The HPC connector on Apollo S10 board can provides 160 use...

Page 26: ...MC_LA_p0 LA00_P_CC CLK_3L_0P J20 FMC_LA_p0 LA00_N_CC CLK_3L_0N J19 Power Supply The Apollo S10 board provides 12V 3 3V and VCCIO_FMC power through FMC ports Table 2 12 indicates the maximum power cons...

Page 27: ...connected to the Stratix 10 FPGA on the FMC connector two of which belong to the GX channels and the maximum transmission speed is 17 4 Gbps The other 8 belong to GXT channels and the maximum transmis...

Page 28: ...1 FMC_CLK2_BIDIR_n PIN_AV17 FMC data bus FMC_VCCIO 1 FMC_CLK3_BIDIR_p PIN_C1 FMC data bus FMC_VCCIO 1 FMC_CLK3_BIDIR_n PIN_D1 FMC data bus FMC_VCCIO 1 FMC_CLK_M2C_p 0 PIN_K5 2 Clock from mezzanine mod...

Page 29: ...k data p15 FMC_VCCIO 1 FMC_HA_p 16 PIN_A9 FMC HA bank data p16 FMC_VCCIO 1 FMC_HA_p 17 PIN_C12 3 FMC HA bank data p17 FMC_VCCIO 1 FMC_HA_p 18 PIN_B11 FMC HA bank data p18 FMC_VCCIO 1 FMC_HA_p 19 PIN_M...

Page 30: ...MC HA bank data n19 FMC_VCCIO 1 FMC_HA_n 20 PIN_G10 FMC HA bank data n20 FMC_VCCIO 1 FMC_HA_n 21 PIN_D9 FMC HA bank data n21 FMC_VCCIO 1 FMC_HA_n 22 PIN_D8 FMC HA bank data n22 FMC_VCCIO 1 FMC_HA_n 23...

Page 31: ...C HB bank data n1 FMC_VCCIO 1 FMC_HB_n 2 PIN_P8 3 FMC HB bank data n2 FMC_VCCIO 1 FMC_HB_n 3 PIN_J5 FMC HB bank data n3 FMC_VCCIO 1 FMC_HB_n 4 PIN_H3 FMC HB bank data n4 FMC_VCCIO 1 FMC_HB_n 5 PIN_H6...

Page 32: ...nk data p7 FMC_VCCIO 1 FMC_LA_p 8 PIN_M9 FMC LA bank data p8 FMC_VCCIO 1 FMC_LA_p 9 PIN_G6 FMC LA bank data p9 FMC_VCCIO 1 FMC_LA_p 10 PIN_E8 FMC LA bank data p10 FMC_VCCIO 1 FMC_LA_p 11 PIN_B6 FMC LA...

Page 33: ...MC LA bank data n1 FMC_VCCIO 1 FMC_LA_n 2 PIN_T10 FMC LA bank data n2 FMC_VCCIO 1 FMC_LA_n 3 PIN_M11 FMC LA bank data n3 FMC_VCCIO 1 FMC_LA_n 4 PIN_U10 FMC LA bank data n4 FMC_VCCIO 1 FMC_LA_n 5 PIN_K...

Page 34: ...n27 FMC_VCCIO 1 FMC_LA_n 28 PIN_K6 FMC LA bank data n28 FMC_VCCIO 1 FMC_LA_n 29 PIN_H1 FMC LA bank data n29 FMC_VCCIO 1 FMC_LA_n 30 PIN_L7 FMC LA bank data n30 FMC_VCCIO 1 FMC_LA_n 31 PIN_R10 FMC LA...

Page 35: ...eiver HSSI DIFFERENTIAL I O FMC_DP_C2M_p 6 PIN_F39 Transmit pair p6 of the FPGA transceiver HSSI DIFFERENTIAL I O FMC_DP_C2M_p 7 PIN_E37 Transmit pair p7 of the FPGA transceiver HSSI DIFFERENTIAL I O...

Page 36: ..._p 7 PIN_J33 Receiver pair p7 of the FPGA transceiver HSSI DIFFERENTIAL I O FMC_DP_M2C_p 8 PIN_F35 Receiver pair p8 of the FPGA transceiver HSSI DIFFERENTIAL I O FMC_DP_M2C_p 9 PIN_G33 Receiver pair p...

Page 37: ...ifference between FMC and FMC specifications is that the number of FMC transceiver can provide up to 24 pairs High Serial Pin Count version HSPC Figure 2 8 FMC connector on Apollo S10 board As the num...

Page 38: ...VADJ 4 pins 3V3 4 pins 12V 2 pins 3V3 Aux 1 pin Clock Interface Table 2 16 shows the FPGA dedicated clock input pin placement on the FMC connector Table 2 16 FMCP clock input interface distribution Si...

Page 39: ...IO_FMCP 4A Adjustable I O Standards The FPGA I O standards of the FMC ports can be adjusted by configuring the header position Each port can be individually adjusted to 1 2V 1 5V or 1 8V via jumper JP...

Page 40: ...and GXT channels on the FMCP connector Transceiver channel Type Net Name Speed GX Channels FMCP_DP_M2C_p2 FMCP_DP_C2M_p2 FMCP_DP_M2C_p5 FMCP_DP_C2M_p5 FMCP_DP_M2C_p8 FMCP_DP_C2M_p8 FMCP_DP_M2C_p11 FM...

Page 41: ...1 FMCP_CLK2_BIDIR_n PIN_AY33 FMCP data bus FMCP_VCCIO 1 FMCP_CLK3_BIDIR_p PIN_AW34 FMCP data bus FMCP_VCCIO 1 FMCP_CLK3_BIDIR_n PIN_AW35 FMCP data bus FMCP_VCCIO 1 FMCP_CLK_M2C_p 0 PIN_ BH36 2 Clock...

Page 42: ...P_VCCIO 1 FMCP_HA_p 13 PIN_AY29 FMCP HA bank data p13 FMCP_VCCIO 1 FMCP_HA_p 14 PIN_BF31 FMCP HA bank data p14 FMCP_VCCIO 1 FMCP_HA_p 15 PIN_BA32 FMCP HA bank data p15 FMCP_VCCIO 1 FMCP_HA_p 16 PIN_BA...

Page 43: ...n16 FMCP_VCCIO 1 FMCP_HA_n 17 PIN_BG32 FMCP HA bank data n17 FMCP_VCCIO 1 FMCP_HA_n 18 PIN_BJ31 FMCP HA bank data n18 FMCP_VCCIO 1 FMCP_HA_n 19 PIN_BE28 FMCP HA bank data n19 FMCP_VCCIO 1 FMCP_HA_n 2...

Page 44: ...data p20 FMCP_VCCIO 1 FMCP_HB_p 21 PIN_BC26 FMCP HB bank data p21 FMCP_VCCIO 1 FMCP_HB_n 0 PIN_AN28 FMCP HB bank data n0 FMCP_VCCIO 1 FMCP_HB_n 1 PIN_AP31 FMCP HB bank data n1 FMCP_VCCIO 1 FMCP_HB_n...

Page 45: ...FMCP_VCCIO 1 FMCP_LA_p 5 PIN_BB37 FMCP LA bank data p5 FMCP_VCCIO 1 FMCP_LA_p 6 PIN_AT38 FMCP LA bank data p6 FMCP_VCCIO 1 FMCP_LA_p 7 PIN_BB39 FMCP LA bank data p7 FMCP_VCCIO 1 FMCP_LA_p 8 PIN_AP34...

Page 46: ...k data p32 FMCP_VCCIO 1 FMCP_LA_p 33 PIN_BE33 FMCP LA bank data p33 FMCP_VCCIO 1 FMCP_LA_n 0 PIN_AW39 FMCP LA bank data n0 FMCP_VCCIO 1 FMCP_LA_n 1 PIN_AR34 FMCP LA bank data n1 FMCP_VCCIO 1 FMCP_LA_n...

Page 47: ...n 25 PIN_BD36 FMCP LA bank data n25 FMCP_VCCIO 1 FMCP_LA_n 26 PIN_BD35 FMCP LA bank data n26 FMCP_VCCIO 1 FMCP_LA_n 27 PIN_BB34 FMCP LA bank data n27 FMCP_VCCIO 1 FMCP_LA_n 28 PIN_BF34 FMCP LA bank da...

Page 48: ...PIN_AK38 FPGA transceiver Reference Clock From on board PLL LVDS FMCP_REFCLK2_p PIN_P41 FPGA transceiver Reference Clock From on board PLL LVDS FMCP_DP_C2M_p 0 PIN_BJ46 Transmit pair p0 of the FPGA t...

Page 49: ...M_p 9 PIN_AW47 Transmit pair p9 of the FPGA transceiver HSSI DIFFERENTIAL I O FMCP_DP_C2M_p 10 PIN_AY49 Transmit pair p10 of the FPGA transceiver HSSI DIFFERENTIAL I O FMCP_DP_C2M_p 11 PIN_AU47 Transm...

Page 50: ...CP_DP_C2M_p 20 PIN_F49 Transmit pair p20 of the FPGA transceiver HSSI DIFFERENTIAL I O FMCP_DP_C2M_p 21 PIN_G47 Transmit pair p21 of the FPGA transceiver HSSI DIFFERENTIAL I O FMCP_DP_C2M_p 22 PIN_E47...

Page 51: ...M2C_p 7 PIN_BB45 Receiver pair p7 of the FPGA transceiver HSSI DIFFERENTIAL I O FMCP_DP_M2C_p 8 PIN_AW43 Receiver pair p8 of the FPGA transceiver HSSI DIFFERENTIAL I O FMCP_DP_M2C_p 9 PIN_AY45 Receive...

Page 52: ..._M2C_p 18 PIN_AF45 Receiver pair p18 of the FPGA transceiver HSSI DIFFERENTIAL I O FMCP_DP_M2C_p 19 PIN_AG43 Receiver pair p19 of the FPGA transceiver HSSI DIFFERENTIAL I O FMCP_DP_M2C_p 20 PIN_G43 Re...

Page 53: ...32 Synchronize signal from carrier card to mezzanine module positive LVDS FMCP_SYNC_M2C_p PIN_AV33 Synchronize signal from mezzanine module to carrier card positive LVDS 1 The FMCP_VCCIO value depends...

Page 54: ...he Stratix 10 SX FPGA can be used to program these two Si5340As to generate FMC and FMC connector reference clock and high bandwidth memory reference clocks respectively One oscillator provides a 125...

Page 55: ...00Mhz VCCIO_FMC PIN_L24 User application Y8 Dual Frequency OSC DDR4A_REFCLK_p 300 266 267Mhz Select by SW5 LVDS DDR4 reference clock for A port U71 Si5341A FMC_REFCLK0_p 644 53125 MHz LVDS PIN_AK12 FM...

Page 56: ...to space constraints The Apollo S10 uses a USB hub to allow USB to UART interface for HPS and FPGA fabric USB blaster II circuit and MAX10 system controller to share a Mini USB connector to connect t...

Page 57: ...bank can run at the fastest clock frequency of 1066MHz clock for a maximum theoretical bandwidth up to 136 4 Gbps Figure 2 11 shows the connections between the DDR4 SDRAM bank and Stratix 10 SX FPGA F...

Page 58: ...DQ19 Data 19 1 2 V POD PIN_H33 DDR4A_DQ20 Data 20 1 2 V POD PIN_H35 DDR4A_DQ21 Data 21 1 2 V POD PIN_H36 DDR4A_DQ22 Data 22 1 2 V POD PIN_F35 DDR4A_DQ23 Data 23 1 2 V POD PIN_J36 DDR4A_DQ24 Data 24 1...

Page 59: ...4A_DQ54 Data 54 1 2 V POD PIN_L27 DDR4A_DQ55 Data 55 1 2 V POD PIN_H26 DDR4A_DQ56 Data 56 1 2 V POD PIN_D26 DDR4A_DQ57 Data 57 1 2 V POD PIN_B25 DDR4A_DQ58 Data 58 1 2 V POD PIN_F27 DDR4A_DQ59 Data 59...

Page 60: ...1 2 V POD PIN_T26 DDR4A_DQS_n4 Data Strobe n 4 DIFFERENTIAL 1 2 V POD PIN_R27 DDR4A_DQS5 Data Strobe p 5 DIFFERENTIAL 1 2 V POD PIN_V28 DDR4A_DQS_n5 Data Strobe n 5 DIFFERENTIAL 1 2 V POD PIN_V27 DDR...

Page 61: ...R4A_A0 Address 0 SSTL 12 PIN_K38 DDR4A_A1 Address 1 SSTL 12 PIN_L37 DDR4A_A2 Address 2 SSTL 12 PIN_M37 DDR4A_A3 Address 3 SSTL 12 PIN_M38 DDR4A_A4 Address 4 SSTL 12 PIN_J39 DDR4A_A5 Address 5 SSTL 12...

Page 62: ...e pin SSTL 12 PIN_K40 DDR4A_ODT0 On Die Termination SSTL 12 PIN_G40 DDR4A_ODT1 On Die Termination SSTL 12 PIN_F40 DDR4A_CS_n0 Chip Select SSTL 12 PIN_G38 DDR4A_CS_n1 Chip Select SSTL 12 PIN_J40 DDR4A_...

Page 63: ...1 2 V POD PIN_BD18 DDR4B_DQ13 Data 13 1 2 V POD PIN_BE21 DDR4B_DQ14 Data 14 1 2 V POD PIN_BB18 DDR4B_DQ15 Data 15 1 2 V POD PIN_BD19 DDR4B_DQ16 Data 16 1 2 V POD PIN_AT19 DDR4B_DQ17 Data 17 1 2 V POD...

Page 64: ..._DQ47 Data 47 1 2 V POD PIN_BB13 DDR4B_DQ48 Data 48 1 2 V POD PIN_BJ16 DDR4B_DQ49 Data 49 1 2 V POD PIN_BJ14 DDR4B_DQ50 Data 50 1 2 V POD PIN_BG14 DDR4B_DQ51 Data 51 1 2 V POD PIN_BH12 DDR4B_DQ52 Data...

Page 65: ...IAL 1 2 V POD PIN_AN21 DDR4B_DQS_n2 Data Strobe n 2 DIFFERENTIAL 1 2 V POD PIN_AP21 DDR4B_DQS3 Data Strobe p 3 DIFFERENTIAL 1 2 V POD PIN_AW21 DDR4B_DQS_n3 Data Strobe n 3 DIFFERENTIAL 1 2 V POD PIN_A...

Page 66: ...Inversion 5 1 2 V POD PIN_BC15 DDR4B_DBI_n6 Data Bus Inversion 6 1 2 V POD PIN_BJ13 DDR4B_DBI_n7 Data Bus Inversion 7 1 2 V POD PIN_BD14 DDR4B_DBI_n8 Data Bus Inversion 8 1 2 V POD PIN_AV13 DDR4B_A0 A...

Page 67: ...F11 DDR4B_CK Clock p DIFFERENTIAL 1 2 V SSTL PIN_BC12 DDR4B_CK_n Clock n DIFFERENTIAL 1 2 V SSTL PIN_BB12 DDR4B_CKE0 Clock Enable pin SSTL 12 PIN_BC10 DDR4B_CKE1 Clock Enable pin SSTL 12 PIN_BB10 DDR4...

Page 68: ...e interface will supply the power to the device through the Micro USB interface Figure 2 12 shows the connections of USB PTG PHY to the HPS Figure 2 12 Connections between the HPS of Apollo S10 and US...

Page 69: ...Gigabit Ethernet PHY and RJ 45 connector For more information about the KSZ9031RN PHY chip and its datasheet as well as the application notes which are available on the manufacturer s website Figure...

Page 70: ...NET_TX_DATA 3 PIN_B32 MII transmit data 3 1 8V HPS_ENET_RX_CTL PIN_F30 GMII and MII receive data valid 1 8V HPS_ENET_RX_DATA 0 PIN_B34 GMII and MII receive data 0 1 8V HPS_ENET_RX_DATA 1 PIN_E31 GMII...

Page 71: ...or and fan speed status These interfaces are connected to the System MAX FPGA on the board The board management logic Dashboard in the system MAX FPGA will monitor these status and perform correspondi...

Page 72: ...Apoolo S10 User Manual 72 www terasic com March 31 2020 Figure 2 15 Block diagram of the system status interface...

Page 73: ...es generated include Quartus Prime Project File qpf Quartus Prime Setting File qsf Top Level Design File v External PLL Controller v Synopsis Design Constraints file sdc Pin Assignment Document htm Th...

Page 74: ...lete the settings the System Builder will generate two major files which include top level design file v and the Quartus Prime setting file qsf The top level design file contains top level Verilog wra...

Page 75: ...ed under the directory Tools SystemBuilder in the System CD Users can copy the entire folder to the host computer without installing the utility Please execute the SystemBuilder exe on the host comput...

Page 76: ...e 3 4 Project Name in the System Builder window Select Top File Type The system builder can generate Verilog or VHDL Quartus top file according to the users requirements Users can select their desired...

Page 77: ...enabled or disabled according to users needs If a component is enabled the System Builder will automatically generate the associated pin assignments including its pin name pin location pin direction...

Page 78: ...rd that provide reference clocks for the following signals DDR4B_REFCLK FMC_REFCLK0 FMC_REFCLK1 FMCP_REFCLK0 FMCP_REFCLK1 FMCP_REFCLK2 DDR4C_REFCLK LVDS_REFCLK To use these clock users can select the...

Page 79: ...rogrammable oscillator Note If users need to dynamically change the frequency they would need to modify the generated control code themselves Figure 3 7 External programmable oscillators Project Setti...

Page 80: ...rtus Prime files and documents as listed in the Table 3 directory specified by the user Table 3 1 Files generated by the System Builder No Filename Description 1 Project name v or Project name vhdl To...

Page 81: ...ment Document The si5340_controller is a folder which contains the Verilog files for the configuration of Si5340A clock generator chips Users can add custom logic into the project and compile the proj...

Page 82: ...Apoolo S10 User Manual 82 www terasic com March 31 2020 The following clock information also be automatically added in sdc file...

Page 83: ...Apoolo S10 User Manual 83 www terasic com March 31 2020 If the dynamic configurations for the Si5340A clock generators are required users need to modify the code according to users desired behavior...

Page 84: ...for detailed The reported status includes FPGA Board temperature fan speed FPGA core power and 12V input power Figure 4 1 shows the block diagram of the Apollo S10 Dashboard Figure 4 1 Block Diagram...

Page 85: ...C Connection Setting 1 Connect the USB Mini USB connector of the Apollo S10 board to the host PC USB port through mini USB cable 2 Connect power to the Apollo S10 board 3 Power on the Apollo S10 board...

Page 86: ...igure 4 3 Uninstalled USB to UART device As described in previous steps copy the device driver to the host PC and install it as shown in Figure 4 4 Please note that the COM Port number is different in...

Page 87: ...s installed successfully 4 2 Run Dashboard GUI Dashboard GUI software location Users can find it from the path Tool dashboard_gui Dashboard exe in the Apollo S10 system CD and copy it to the host PC E...

Page 88: ...igure 4 7 there is a Start button at the bottom left of the GUI window Click it to run the program Start will change to Stop it will show the Apollo S10 board status Users can press Stop button to sto...

Page 89: ...it will show the status LED number on the Apollo S10 board For these LEDs function please refer to section 2 2 Note that MAX_CONF_DONE stands for FPGA configure done status There is no LED on Apollo S...

Page 90: ...ction FPGA Board Temperature The Dashboard GUI will real time show the fan speed Apollo S10 board ambient and FPGA temperature Users can know the board temperature in time The information will be refr...

Page 91: ...Apoolo S10 User Manual 91 www terasic com March 31 2020 Figure 4 9 Temperature section Fan RPM It displays the real time speed of the fan on the Apollo S10 board as shown in Figure 4 10...

Page 92: ...User Manual 92 www terasic com March 31 2020 Figure 4 10 FAN RPM section 12V Core Power monitor It displays the real time 12V Core Power 0 9V voltage and consumption current on the Apollo S10 board a...

Page 93: ...1 2020 Figure 4 11 Power Monitor Section Sampling Speed It can change interval time that the Dashboard GUI sample the board status Users can adjust it to 1s 10s 1min Full Speed 0 1s to sample the boar...

Page 94: ...pling Speed section Figure 4 13 Options of Sampling Speed Board Information There is a File page on the upper left of the Dashboard GUI program window click the Board Information to get the current so...

Page 95: ...File On the upper left of the Dashboard GUI program window click the Export in the File page to save the board temperature fan speed and voltage data in csv format document as shown in Figure 4 15 and...

Page 96: ...ere are the addresses where you can get help if you encounter problems Terasic Technologies 9F No 176 Sec 2 Gongdao 5th Rd East Dist HsinChu City Taiwan 30070 Email support terasic com Web www terasic...

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