Apoolo-S10
User Manual
16
www.terasic.com
March 31, 2020
SoC FPGA boot
The boot process for Stratix 10 SoC FPGAs can be divided into two different methods:
FPGA Configuration First Mode
HPS Boot First Mode
The difference between the two methods is the initial difference between HPS and
FPGA fabric after powering on. More details can be found in the user documentation:
Intel Stratix 10 SoC FPGA Boot User Guide
The factory setting of the SoC boot of the Apollo S10 board is the
FPGA
Configuration First Mode
. The architecture is shown in the
. Two storage
mediums are used. The system needs QSPI flash on Apollo S10 as SDM flash for
booting.
Figure 2-3
FPGA Configuration First Dual SDM and HPS
Flash
The QSPI flash memory has the following boot data for the first part of the SoC FPGA
configuration:
Configuration firmware for the SDM
FPGA I/O and HPS external memory interface (EMIF) I/O configuration data
FPGA core configuration data
HPS First-Stage Boot Loader(FSBL) code and FSBL hardware handoff binary
data
