Terasic Apollo S10, User Manual

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Apoolo-S10
User Manual 23 www.terasic.com
March 31, 2020
Table 2-7 lists the signal names and their corresponding Stratix 10 SX device pin
numbers.
Table 2-7 Dip Switch Pin Assignments, Schematic Signal Names, and Functions
Board
Reference
Schematic
Signal Name
Description
I/O
Standard
Stratix 10 SX
Pin Number
SW0 SW0 High logic level when SW in
the UPPER position.
3.0-V LVTTL PIN_AG35
SW1 SW1 3.0-V LVTTL PIN_AH33

User-Defined LEDs
The FPGA board consists of 2 FPGA fabric and 1 HPS fabric user-controllable LEDs to
allow status and debugging signals to be driven to the LEDs from the designs loaded
into the Stratix 10 SX device. Ea ch LED is driven directly by the Stratix 10 SX FPGA.
The LED is turned on or off when the associated pins are driven to a low or high logic
level, respectively. A list of the pin names on the FPGA that are connected to the LEDs
is given in Table 2-8 . Table 2-9 list the information of the LED for the HPS fabric.
Table 2-8 User LEDs (FPGA fabric) Pin Assignments, Schematic Signal Names,
and Functions
Board
Reference
Schematic
Signal Name
Description I/O Standard
Stratix 10 SX
Pin Number
LED0 LED0 Driving a logic 0 on the
I/O port turns the LED
ON.
Driving a logic 1 on the
I/O port turns the LED
OFF.
3.0-V LVTTL PIN_AH32
LED1 LED1 3.0-V LVTTL PIN_AC33
Table 2-9 User LEDs (HPS fabric) Pin Assignments, Schematic Signal Names,
and Functions
Board
Reference
Schematic
Signal Name
Description
I/O
Standard
Stratix 10 SX
Pin Number