Apoolo-S10
User Manual
54
www.terasic.com
March 31, 2020
Figure 2-9 Clock circuit of the FPGA Board
A clock buffer is used to duplicate the 50 MHz TCXO output clock, so there are two
50MHz clocks fed into different two FPGA banks. The two programming clock
generators with low-jitter clock outputs are used to provide special and high- quality
clock signals for high-speed transceivers and high bandwidth memory. Through I2C
serial interface, the clock generator controllers in the Stratix 10 SX FPGA can be used
to program these two Si5340As to generate FMC and FMC+ connector reference clock
and high bandwidth memory reference clocks respectively. One oscillator provides a
125 MHz clock used as configuration clock or used as the clock for transceiver
calibration.
In addition, the reference clock (DDR4A_REFCLK_p) for DDR4A can be selected by a
dual frequency OSC to the FPGA. For details, please refer to the "DDR4A Reference
Clock Switch" part in the section 2.2.
Table 2-20 Clock source and clock pin to the FPGA
Source
Schematic
Signal Name
Default
Frequency
I/O
Standard
Arria 10
GX Pin
Number
Application
U16
CLK_50_B2F
50.0 MHz
VCCIO_FMC PIN_BA27
User
