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T3PSX3200P Series User Manual
182
In general it is best to use the Operation Complete Bit (bit 0) in the
standard event register to check to see if an operation/command
has completed. After executing the *OPC command, the OPC bit
will be set to 1. If a command or query is placed in the output
buffer immediately before the *OPC command is sent, the
Operation Complete Bit can be used to determine when the
information can be used. However if too many commands/queries
are executed prior to the execution of the *OPC command, the
output buffer could become saturated and the unit will stop taking
readings.
Standard Event Register
The Standard Event Register reports the following types or events:
Power on has been detected, command syntax errors, command
execution errors, self test and execution errors, query errors or if the
*OPC command is executed. Any one or more of these events will
set the standard event summary bit in the status byte register. To
set a mask for the enable register, a binary-weighted decimal
number must be written using the *ESE command.
Summary of Contents for T3PS13206P
Page 1: ... ...
Page 106: ...T3PSX3200P Series User Manual 106 Register Commands OPC 187 OPC 187 ...
Page 177: ...REMOTE CONTROL 177 Example SAV 1 Recalls the setting stored in memory 2 STATE02 ...
Page 185: ...REMOTE CONTROL 185 Example STB Returns 81 if the status byte register is set to 0101 0001 ...
Page 196: ...T3PSX3200P Series User Manual 196 Between chassis and DC power cord 30MΩ or above DC 500V ...
Page 197: ... 0 0 0 1 2 3 4 5 6 7 8 8 9 3 3 3 45 6 990 0 0 9 0 0 0 9 0 0 0 0 9 7 7 88 8 1 931711 RevB ...