Tektronix RSA3300A, Service Manual

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Theory of Operation
3- 4
RSA3303A & RSA3308A Service Manual
The Trigger Detector achieves real-time frequency trigger function. When the
Frequency Mask Trigger function is activated, window function operation is
executed to the input signal first. To accelerate the operation, data are divided
into two groups: the odd frame data and the even frame data. With pipeline-con-
nected FFT processors, real-time FFT is applied to these groups of data. After
being converted into frequency domain, the data are further converted into the
power domain with a pipeline-connected quadrature-to-polar coordinates
converter. After comparison with the reference data, the trigger board outputs the
trigger detect signal. When the Power Trigger function is activated, window
function operation and FFT operation mentioned above are bypassed. The data of
the time domain are converted into the power domain and sent to Trigger
Comparator.
The Acquisition Memory saves time domain data separated into I and Q signals.
The A40 DIFP board also interfaces between the data block and Windows
system. I/Q data output from the digital filter is saved to the dual port SRAM,
and then transferred to SDRAM as a block of data. The memory block of
SDRAM is also connected to the PCI local bus via a different dual port SRAM.
This allows the Windows system to refer to the contents copied to this dual port
SRAM as the data on the PCI memory space. The TRIG IN and OUT connectors
located on the rear panel are connected with this board. An external trigger signal
input is used, in addition, as the timing reference signal for the address control-
ler. The A40 board also contains a microprocessor that controls various software
settings and various types of hardware as well as peripheral devices such as
ROM/RAM.
The DDC board consists of an IQ Splitter and cascade-connected Digital Filters.
After being converted into digital format in the A10 A/D board, the input signal
is split into I and Q signals by the IQ Splitter. At the same time, I/Q signals are
frequency-shifted so that each of them occupies a frequency band centered at
frequency zero point (DC). I/Q signals output from IQ Splitter are sent to the
Digital Filters. In these filters, bandwidth of these signals is limited correspond-
ing with span settings. In addition, resampling is performed to achieve the higher
frequency resolution. I/Q signals output from the Digital Filters are sent to the
A30 Trigger board (optional) and the A40 Memory board.
In the A20 DDC board, the IF Level Trigger signal is generated based upon the
data output from the A/D converter. The trigger signal is sent to the A40
Memory board that stops data acquisition at the timing corresponding with
trigger position.
A20 DDC Board
S/N below B020000 and
J300100 and above