Tektronix RSA3300A, Service Manual

Page: 51 / 284

Theory of Operation
RSA3303A & RSA3308A Service Manual
3- 3
The 10 MHz Reference Oscillator is configured around an OCXO (Oven
Controlled Crystal Oscillator) with extremely high frequency stability. It is used
as the reference clock source for all the oscillators including the frequency
synthesizer circuits.
Circuits such as the input circuit of external 10 MHz reference signal, internal/
external reference switching circuit, and 10 MHz reference output circuit are also
contained in the RF5 module.
The RF4 module is comprised of synthesizer circuits. The synthesizer consists of
multiple PLL Oscillator units of low noise type locked with the 10 MHz
reference signal. By changing the oscillation frequency of these PLL Oscillator
in fine steps, 1
st
LO frequency can be tuned in the range of 4 GHz to 8 GHz
while maintaining a good level of C/N.
The synthesizer also contains a circuit for generation of a 50 MHz signal to be
used as the reference for the calibration signal, PLL circuitry of the 2
nd
Local
Oscillator, a circuit for generation of DDS signal to be used as the reference
signal for the 3
rd
Local Oscillator, and other components.
Digital Signal Processing
Analog signals such as the IF signal sent from the Down Converter block are
converted into digital format with a high-speed, high-accuracy A/D converter,
and sent to the A20 DDC board via the A50 Mother board.
The A/D board contains input circuits for three analog signals: IF signal,
baseband signal, and external IQ signal (optional). Each input circuit is equipped
with a Buffer Amplifier, a Step Amplifier, and a Step Attenuator to maintain the
signal level as appropriate, as well as a BPF or LPF for removal of signal
components within unnecessary frequency bands.
The A40 DIFP (Digital IF Processor) board consists of an IQ Splitter, Digital
Filters, Trigger Detector, and Acquisition Memory. After being converted into
digital format in the A10 A/D board, the input signal is split into I and Q signals
by the IQ Splitter. At the same time, I/Q signals are frequency-shifted so that
each of them occupies a frequency band centered at frequency zero point (DC).
I/Q signals output from IQ Splitter are sent to the Digital Filters. In these filters,
bandwidth of these signals is limited corresponding with span settings. In
addition, re-sampling is performed to achieve the higher frequency resolution.
I/Q signals output from the Digital Filters are sent to the Trigger Detector and
Acquisition Memory.
RF4 Module
A10 A/D Board
A40 DIFP Board
S/N B020000 and above