Tektronix 2230, Service Manual

Page: 79 / 483

Theory of Operation— 2230 Service
actual clocking that occurs depends on the sampling mode
(Min/Max, Sampling, or X-Y). The same waveform data is
also applied to opposite comparator inputs of two eight-bit
magnitude comparators. Output data from the Min and
Max Registers is applied to the other comparator’s input
pins, with the Min Register data going to the Min Com­
parator and the Max Register data going to the Max
Comparator.
In Min/Max mode, the first data byte taken in a sample
window (set by the SEC/DIV switch setting) is clocked into
both registers. That data byte is then compared with the
next data sample or samples (determined by the sample
window) being applied to the inputs of the Min and Max
Registers. If the data byte is either smaller in magnitude
than the last clocked minimum or greater in magnitude
than the last clocked maximum, a NEWMIN or a
NEWMAX signal is generated. The signal is routed through
the Min/Max Clock Selector back to the clock input of the
Min or Max Register (Min if it is a new minimum amplitude
or Max if it is a new Maximum amplitude) and the new sig­
nal is clocked into the register. At the end of a Min/Max
sample window, the data present at the output of the Min
and Max Registers is clocked into the Swap Registers to
be transferred to the Acquisition Memory.
When record sampling mode is selected, each
waveform sample is successively clocked into the Min and
Max Registers on alternate ODDCLK and ODDCLK sig­
nals. When X-Y mode is selected, the Channel 1 and
Channel 2 waveforms are sampled in a chopped manner,
with samples of the two channel signals being taken with
less time between the samples than in normal record sam­
pling mode. Channel 1 data is clocked into the Min Regis­
ter, and Channel 2 data is clocked into the Max Register.
Four eight-bit Swap Registers are used to reorder the
Max and Min data obtained from each sample window.
The Max Register data is clocked into two of the registers
in parallel, and the Min Register data is clocked into the
other two registers in parallel. The Min and Max data out­
put from one of the Swap Registers in each set of two is
applied to two busses going to the Acquisition Memory. If
the Max and Min data is to be reversed to maintain the
correct time order of the samples before being stored, the
alternate swap register in each set of two is enabled, and
the Max and Min data is applied to the opposite busses to
memory.
Acquisition mode is controlled in part by the Micropro­
cessor via data latched into the Acquisition Mode Register
(see also, “ Time Base Mode Register" in this section).
These data bits select the channel or channels to be
acquired, enable the XY mode, enable MIN/MAX acquisi­
tion, control the Swap function for reordering data, and
select the Test function for diagnostics. Acquisition clock
signals generated by the Acquisition Clock Decoder
transfer the data from stage to stage in the digital acquisi­
tion circuitry in a pipe-line fashion.
A Diagnostics Code Generator is included as a trouble­
shooting aid. When in the Test mode, the A/D Buffer is
disabled, and the Code Generator places its counter­
output bytes on the input bus to the Max and Min
Registers.
Acquisition Memory
The Acquisition Memory is composed of two, 2-K by 8-
bit random-access memory devices. One memory stores
the Odd data bytes and the other stores the Even data
bytes. The Odd and Even data can be swapped between
the Swap Registers and the Acquisition Memory.
A programmable address counter is loaded with the
number that is the amount of pretrigger data bytes needed
to fill the pretrigger portion of the waveform acquisition.
The PREFULL signal is sent to the Trigger Mux circuitry
when the pretrigger count is full. That signal enables the
Trigger Mux circuitry to accept a trigger signal. The
remaining output bits from the Address Counter select the
storage location for waveform data storage in the Acquisi­
tion Memory.
When waveform data is to be read out of the Acquisi­
tion Memory, the Address Counter is loaded with the
address cf the data for the waveform. The Microprocessor
sequences through the addresses reading out the data
bytes. Data transceivers allow data to be read from the
memory to the bus or written from the bus to the memory.
Memory Address Registers place the address count on
the bus along with bits that indicate the trigger status
(TRIGD), the B trigger status (BTRIGD), the end-of-record
status
(ENDREC), and the byte-interrupt status
(BYTEINT). These accompanying bits are used in estab­
lishing display attributes.
Memory writes, memory reads, and address counter
load enabling and clocking are controlled by a quad, two-
line-to-one-line multiplexer (Memory Control). Read and
write signals from the Microprocessor control bus and
write clocks are used to transfer the waveform data
between the devices.
Digital Time Base
An accurate frequency source for synchronizing the
Microprocessor with the other digital devices on the bus is
provided by a 40 MHz oscillator. That frequency is divided
3-5