Tektronix 2230, Service Manual

Page: 106 / 483

Theory of Operation— 2230 Service
function of the SEC/DIV switch setting). As the SAVECLK
period increases with slower SEC/DIV switch settings, the
number of samples compared to find a min and a max per
SAVECLK period also increases.
MIN-MAX OUTPUT. One CONV clock period before the
end of the SAVECLK period, the ACQWRITE signal gives
write control of the Acquisition Memory to the acquisition
system (see Figure 3-8). If SWAPEN (U3320 pin 13) is HI,
either SWAP (U3313A pin 3) or SWAP (U3313B pin 6)
becomes TRUE (depending on whether the last sample
was a NEWMAX or a NEWMIN) at one-half a CONV clock
period before the end of the SAVECLK to enable the out­
put of one set of the Swap Registers onto the memory
data buses. At the same time, BUFFERCLK (U3103A
pin 5) goes HI to clock the last Min and Max data from the
MIN/MAX Registers into and through the Swap Registers
onto the memory data buses where the data is written into
the Acquisition Memory. All 16 bits of the Min and Max
data are transferred into memory in parallel. This 16-bit
transfer also holds true for Odd and Even or Channel 1
and Channel 2 data bytes when those signals are being
sampled.
Acquisition Mode Register
The Acquisition Mode Register controls the manner in
which data is transferred through the acquisition system
from the A/D Buffer to the Acquisition Memory. Outputs of
the MIN/MAX Clock Selector multiplexer, U3309, were dis­
cussed in the description of the MIN/MAX Registers. The
control signals for switching the multiplexer and selecting
which set of Swap Registers are enabled when transfer­
ring data to the Acquisition Memory are described in this
part. The mode selection control of the MIN/MAX Clock
Selector multiplexer is shown in Table 3-2.
Table 3-2
MIN/MAX Clock Selector Multiplexer Switching
MODE
Control
Input 0
Control
Input 1
Input
Selected
MIN/MAX INIT 1 1 3
MIN/MAX 0 1 2
SAMPLING
1 0 1
SAMPLING XY 0 0
0
__ Multiplexer switching is controlled by the MIN/MAX and
XY signals from the Acquisition Mode Register U3310
(sent by the Microprocessor) and the state of the CONV
clock. In MIN/MAX, the circuitry composed of U3306A and
U3306B produces a 100 ns HI pulse at the beginning of
each SAVECLK cycle to initialize the MIN/MAX Registers
for making comparisons. Prior to entering the Min/Max
mode, flip-flop U3306A is held in the Set state (reset is
also LO, so both outputs of the flip flop are HI). Each ris­
ing CONV clock edge clocks the HI through flip-flop
U3306B and pin 9 remains HI. With a LO MIN/MAX signal
on control input 1 and a HI from flip-flop U3306B on con­
trol input 0, the multiplexer selects the sampling mode
clocks (ODDCLK and ODDCLK) to clock data into the
MIN/MAX Registers.
When MIN/MAX (U3310 pin 14) goes HI, the set is
removed from U3306A and the flip-flop becomes reset by
the LO on pin 1. On the next rising edge of CONV, the LO
is clocked through flip-flop U3306B, and the reset is
removed from U3306A. On the next rising edge of
EVENCLK, the fixed HI on the D input of U3306A is
clocked through that flip-flop to the D input of U3306B.
Then on the next rising edge of CONV, it is clocked to the
Q output to make control input 0 of the multiplexer HI
along with the MIN/MAX input on control input 1. The mul­
tiplexer will not yet pass the fixed HI inputs selected,
because the outputs are not enabled. When CONV goes
LO, AND-gate U4101C passes that LO to the enabling
inputs of the multiplexer. The two input HI levels are then
passed through the multiplexer to clock the same data
byte into both MIN/MAX Registers. When CONV again
goes HI, the multiplexer outputs become disabled, so the
1NIT clock to the MIN/MAX Registers last for only one-half
of a CONV clock period.
When the HI was clocked to pin 9 of U3306B, pin 8
went LO, and U3306A became reset, placing a LO on its
Q output. The next rising edge of the CONV clock clocks
the LO through flip-flop U3306B, changing control input 0
of the multiplexer and removing the reset from flip-flop
U3306A. The initialization pulse to control input 0 lasts for
a period of one CONV clock; 100 ns in Min/Max mode.
After initialization, the multiplexer switches to select the
NEWMIN and NEWMAX outputs from the data compara­
tors (U3233 and U3235) to clock the MIN/MAX Registers.
The one-half CONV clock delay in enabling the multiplexer
allows the outputs of the Comparators to settle when, on
the next samples, the outputs of the comparators are
used to clock the MIN/MAX Registers. A new initialization
is started again on the next rising edge of EVENCLK (once
for each SAVECLK).
The last Acquisition Mode is XY Sampling. The
Microprocessor sets the MIN/MAX and XY signals LO at
the Acquisition Mode Register (U3310). That places a LO
on control input 1 of the multiplexer and en_ables the out­
puts through AND-gate U4101C. With XY LO, flip-flop
U3306B is held reset, placing a LO on control input 0 of
the Multiplexer. The MINCLK and MAXCLK are then the
EVENCLK and ODDCLK signals respectively. These
clocks produce the minimum possible time difference
(100 ns) between the Channel 1 and Channel 2 data sam­
ples that are stored as a pair.
3 -3 2