Tektronix 2230, Service Manual

Page: 207 / 483

Maintenance— 2230 Service
An acquisition is run as in HS_ACQ except that U4103B
selects an input that makes RECCLK a submultiple of
CONV clock. As in HS_ACQ, ENDREC is polled and the
Post Record Counter and Acquisition Memory completion
values are checked. Although the acquisition is similar to
the HS ACQ acquisition, the fill is different (see
Table 6-12).
NOTE
See Table 6-12, (Diagnostic Acquisition Values) for
specific signals, register values, and terms used in
the following discussion.
If the SELECT C1/C2 button is held in while the test is
running, the test loops on the first error. If an error is
detected, one of the following messages is displayed on
the crt:
TBD < rn g > : < e rro r>
Where:
Rng is one of the following:
hs/2
ps/2
ps/5
ps/10
/10
/100
/Ik
/10k
/100k
Error is one of the following:
latent END_OF_RECORD
prc <prc_actual> < > <prc_expected>
acq_mem cntr <mem_actual> < >
< mem_expected >
fill @ <address> : <fill_actual> < >
<fill_expected>
MM_ACQ. This test checks the acquisition circuitry as
it relates to MIN/MAX.
NOTE
This test also runs the XY_ACQ test.
RECCLK is set using the Time Base Divider to 1/200th
of the CONV clock. Then an acquisition is performed as in
HS ACQ, ENDREC is polled, and the Post Record Counter
and Acquisition Memory Counter completion values are
checked.
Fill testing starts at acq_mem address 0000. The fill is
tested for max (odd) byte minus min (even) byte to give
either 255 or 200.
NOTE
The error message values are as in HS_ACQ except
for the fill values.
If an error is found, one of the following messages is
displayed on the crt:
MM_ACQ : latent END_OF_RECORD
MM_ACQ : prc <prc_actual> < > <prc_expected>
MM_ACQ : acq_mem cntr <acq_mem_actual> < >
< acq_mem_expected >
MM_ACQ : fill @ <fill_address> : <fill_actual>
< > <fill_expected>
XY_ACQ. This test checks the acquisition circuitry as it
relates to X-Y.
NOTE
This test has no menu entry, however it is run by
MM_ACQ.
As in HS_ACQ, an acquisition is performed, ENDREC
is polled, and the Post Record Counter and Acquisition
Memory Counter completion values are checked. The fill is
tested for n, n+1, n+4,n+5, n+8, n+9, ... starting at
Acquisition Memory address 0000.
NOTE
The test and the error message values are as in
HS_ACQ except for the fill values.
If an error is found, one of the following messages is
displayed on the crt:
XY_ACQ : latent END_0F_RECORD
XY_ACQ : prc <prc_actual> < > <prc_expected>
XY_ACQ : acq_mem cntr <acq_mem_actual> < >
<acq_mem_expected>
XY_ACQ : fill @ <fill_address> : < fill_actual> < >
<fill_expected>
CDT. This test checks the Clock Delay Timer. The CDT
(clock delay timer) is a dual-slope integrator used to 1
6-26