Tektronix 2230, Service Manual

Page: 117 / 483

Theory of Operation— 2230 Service
Table 3-5
Trigger Logic Multiplexer Switching
CALTIMER A/BTRIG TEST TRIGGER MODE SELECTED SIGNAL
0
0 1 A TRIG
A GATE
0 1 1 B TRIG B GATE
1 0 0 MIN COUNT CONV
1 1 1 MAX COUNT CONV
must know the information to place the data samples into
the correct locations in Display Memory. Since the trigger
is asynchronous to the CONV clock (and therefore to the
SAVECLK that stores data byte pairs into the Acquisition
Memory), no fixed timing relationship exist between the
trigger and the data samples taken as a result of the
trigger. Therefore the relationship must be determined for
each trigger in equivalent-time sampling.
The timer is formed by a dual-slope capacitor charging
circuit. A fast-charging current source composed of Q4203
and Q4204 charges capacitor C4201 when FET Q4207 is
turned off, removing its shunting effect (short) from the
capacitor. This happens for every A GATE or B GATE
(depending on which trigger it is looking for) regardless of
whether a STORE mode trigger is enabled or not. If a
STORE mode trigger was not enabled, the capacitor is
immediately discharged when the gate signal passes. If a
STORE mode trigger is enabled (PREFULL generated from
the acquisition memory Address Counter), Q4207 is held
off to allow C4201 to continue to charge. The fast­
charging current source through Q4204 is then shut off by
the second_rising edge of the CONV signal clocking a LO
onto the Q output of flip-flop U4226B. The LO turns
Q4203 on and shuts off the fast-charging current source,
Q4204. The complementary HI on the Q output of U4226B
also removes the reset from the Clock-Delay-Timer
counter, U4230, enabling the counter to count.
A slow-charging current source (Q4205 and associated
resistors) then begins discharging C4201 towards the
-8 .6 V supply through Q4205 and R4212. This discharge
path has a long time constant so that the discharge time
is much longer than the capacitor's charge time. The volt­
age on C4201 is applied to the inverting input of compara­
tor U4229. A comparison voltage with a threshold of about
0.6 V is on the noninverting input of the comparator.
When the capacitor’s voltage drops to the comparison
voltage, the output of the comparator goes HI. That HI is
applied to NAND-gate U4106, the Set input of flip-flop
U4232A. The flip-flop has been toggling on the CONV
clock, so depending on the state of the Q output when the
comparator changes state, the flip-flop will either be set
immediately (if the Q state is HI) or as soon as the logic
state of the Q output of U4232A goes HI. The action of
the NAND-gate ensures that the flip-flop becomes set
within ±1 CONV clock period of the actual comparator
output level change. As soon as U4232A becomes set, a
LO is placed on the D input of flip-flop U4232B. On the
next rising_edge of the CONV clock, the LO is clocked to a
HI on the Q output of U4232B, stopping the Clock-Delay-
Timer counter. The count now held in the counter is a
measure of the time between the trigger point and the
next rising edge of the CONV clock. In I/O period 10-1,
address line A3 is made LO by the Microprocessor, ena­
bling the count onto the data bus so the count can be
read. The count is used by the Microprocessor to place
the equivalent-time data samples into the correct (in rela­
tion to the trigger) display memory locations.
In order for the Microprocessor to place the data sam­
ples into the correct display locations, the Microprocessor
needs to know the maximum and minimum counts pro­
duced by the Clock Delay Timer. A calibration routine in
the Diagnostics determines the maximum and minimum
counts and calculates the calibration constant used by the
equivalent-time sampling firmware.
To determine the maximum count, CONV is selected as
the trigger source (U4227 pins 12 and 13). The trigger
source, through U4228A, U4127, and Q4207 starts the
ramp on C4201. The CONV trigger also propagates
through U4228A, U4228B, U4127C, and U4226B to
Q4203, stopping the current source for the ramp and
removing the clear on counter U4230 pin 10. Counter
U4230 starts counting and contains the maximum count
when stopped by CONV through U4232.
To determine the minimum count, CONV is also
selected as the trigger source. The trigger, through
U4228A, starts the ramp on C4201. The calibration routine
sets
TEST
LO. With TEST LO (on U4228B pin 10), CONV
bypasses U4228B, stopping the current source for the
ramp, starting counter U4230 50 ns sooner.
3-43