Tektronix 2230, Service Manual

Page: 266 / 483

Options— 2230 Service
OPTION 10
THEORY OF OPERATION
The General Purpose Interface Bus (GPIB) option (see
Diagram 24) provides a general purpose interface for the
exchange of waveform data and instrument-state informa­
tion. It retains the XY Plotter function of the base instru­
ment, and provides a means of adding non-volatile
waveform memory.
The XY Plotter circuitry is unchanged from the standard
instrument. The circuit descriptions covering the standard
XY Plotter still apply, and are not repeated here. The fol­
lowing discussion refers only to the GPIB
portion of the
board.
The board contains 64K bytes of ROM, 2K bytes of
RAM, and an interface to the GPIB port. Supporting the
GPIB port are two 8-bit input ports for status signals and
parameter switches, and a 1-bit output port used for diag­
nostics. The remainder of the circuitry provides signal
buffering and address decoding.
The microprocessor bus extends to this option through
W8101. The address bus, the data bus, the bus control
signals, and several address decode lines which are gen­
erated on the storage board are included. Power supplies
are also brought in through this connector,
and
J9301 in
the XY Plotter portion of the board is not used.
Bus Buffers
The address lines are buffered by U1341 and U1333.
The buffers are always enabled. Bidirectional data bus
buffer U1331 isolates the circuitry from the storage board
and provides improved signal drive capability. Also
buffered are the RD, WR, 6.7MHZCLK, and RESET
signals.
Address Decoding
The GPIB occupies all of the addresses in the COM-
SEG range (80000H to BFFFFH). Its I/O occupies several
addresses in the l/O-SEG range (40000H to 7FFFFH).
Table 3-1 lists the actual addresses used.
Primary address decoding is accomplished by U1345. It
provides a one-of-eight, active-LO signal when BA12,
BA13,10 SEG, and BLKO, are all LO. Three address lines,
BA3, BA6, and BA7, are decoded to produce the eight
strobes. Four of the strobes enable the GPIB controller
U1351, Parameter buffer U1322, Status buffer U1323, and
Diagnostic latch U1335. Also generated by U1345 is a sig­
nal that is LO whenever one of the strobes is enabled and
BA8 is LO. This signal is gated with COM SEG and DEN
in U1332 to produce an enable for data buffer U1331 via
U1344C.
Half of U1332 generates the ROM enable signal. The
ROM is enabled whenever COM SEG is LO and either
BLKO or BLK1 is LO. This enable drives the output enable
(pin 22) of U1343 and not its chip enable (pin 20) which is
driven by A18.
The other half of U1332 generates the DATEN enable
for the data bus buffer. When DEN is LO and either
I/O 20 PT or COM SEG is LO, pin 8 of U1332 goes HI.
U1344 inverts this signal, producing DATEN. The data bus
buffer is enabled only for references in COM SEG or to I/O
ports used by this option.
The RAM enable signal RAMEN (U1334A pin 3) is pro-
duced by U1334A and U1334C. RAM enable RAMEN is
LO only if RAM DIS, BLK3, and COM SEG are all LO.
RAM DIS disables U1342 if the non-volatile RAM is
present.
RAM and ROM
Temporary storage for the option is provided by RAM
U1342. Option operating system firmware is contained in
ROM U1343.
GPIB Controller
The GPIB controller, U1351, is a TMS9914A which
handles much of the protocol required to interface to the
IEEE STANDARD 488 bus. The controller has eight inter­
nal registers decoded by RSO, RSI, and RS2. Linder cer­
tain conditions it generates an interrupt to the micropro­
cessor which appears as a LO INT (U1351 pin 9). This pin
is an open drain output connected to the microprocessor's
maskable interrupt.
Data bus lines are reversed, BDO for BD7, to accom­
modate the internal convention of the GPIB controller.
Trigger signal TR, U1351 pin 39, is used only for diag­
nostics and is read by the microprocessor via U1322 pin 2.
Line Drivers
Bus buffers U1324 and U1325 provide the drive charac­
teristics required by IEEE 488 bus standards. They also
control characteristics of the drive circuitry during bus
operation.
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