Theory of Operation— 2230 Service
trigger signal to the Trigger Amplifier when internal trigger
ing is selected. Other signal pickoffs provide vertical
position information to the Position Signal Conditioning cir
cuitry for vertically positioning the stored signal. The final
stage of the Vertical Preamplifier for each channel pro
vides one of two signals; either the vertical channel signal
for the analog presentation on the crt or the vertical
acquisition signal to be digitized by the storage circuitry.
Channel signals either for direct analog presentation on
the crt or for application to the Storage digitizing circuitry
are selected by the analog Channel Switch under control
of the front-panel VERTICAL MODE switches. The switch
ing signals from the Channel Switch Logic control a diode
gate (Channel Switch) that selects the channel signal(s) to
be applied to the Delay-line Driver. If ADD is selected, both
channel signals are applied to the Delay-line Driver where
the signals are summed together. The Delay-Line Driver
provides the proper signal-driving level and impedance
match to the Delay Line, where the vertical signal is
delayed approximately 100 ns with respect to the trigger
signal. The vertical signal delay allows time for the Hor
izontal circuitry to start the sweep before the vertical sig
nal is applied to the crt.
Whenever STORE mode is selected, analog signals
from the Storage circuitry are supplied to the Channel
Switch circuit. Linder control of the Channel Switch Logic,
which is in turn switched by signals from the Display Con
troller, the analog display signal out of the final Vertical
Preamplifier stage in each channel is biased off. The Chan
nel 1 and Channel 2 Acquisition signals from the final
preamplifiers are then biased on to pass the signals to be
digitized to the Storage circuitry. At the same time, the
Channel Switch (diode gate) is switched to pass the
Storage vertical signal to the Delay Line Driver input.
Final amplification of the vertical signal (either STORE
or NON STORE) is done by the Vertical Output Amplifier.
This stage produces the signal levels that vertically deflect
the crt electron beam. This amplifier stage also contains
the vertical trace separation circuitry that separates the
Nonstore A Intensified trace from the B Delayed trace
when Alt Horizontal display mode is selected. The amount
of trace separation is controlled using the front panel
TRACE SEP knob. Another circuit feature in the Vertical
Output Amplifier is the nonstore bandwidth limit (BW
LIMIT) circuitry that follows the Delay Line. Either the full
100 MHz bandwidth or the limited 20 MHz bandwidth for
the nonstore signal display may be selected. STORE mode
signals are picked off in the Preamplifier and are not
bandwidth limited by the BW LIMIT switch.
Triggering
The Triggering circuitry uses either the Internal Trigger
signal obtained from the input signal(s), an External
Trigger signal, or a Line Trigger signal derived from the
ac-power-source to develop trigger signals for the Sweep
Generator. The Auto Trigger circuit sets the range of the
Trigger Level to conform approximately to the peak-to-
peak amplitude of the selected trigger signal when either
Auto or TV Field Trigger mode is selected. In Norm mode,
the TRIGGER LEVEL control must be adjusted to the sig
nal level before a sweep will be triggered. ROLL Storage
(selectable at the slower sweep speeds in STORE mode)
overrides the triggering circuit functions; a continuous sig
nal acquisition is made and the signal displayed without
the need of a trigger signal.
The triggering circuitry contains the TV Field Sync cir
cuit. This circuit provides stable triggering on television
vertical-sync pulses when in the TV Field triggering mode.
TV Line triggering is possible using P-P AUTO trigger
mode.
Signal pickoffs from the Internal Trigger circuitry pro
vide the X-Axis signal for the nonstore X-Y display mode
and the B trigger signal for triggered B Sweeps:
A Sweep
The A Sweep Generator and Logic circuits control the
nonstore sweep generation and both the Store and the
nonstore A Sweep timing. When the A TRIGGER mode
switches are set to either P-P AUTO or TV FIELD and no
trigger signal is present, the Auto Baseline circuit causes
the Sweep Logic circuit to produce a sweep for reference
purposes. In the NORM setting, the Auto Baseline circuit
is disabled and nonstore sweeps are not generated until a
trigger event occurs. NORM trigger mode is used to obtain
stable triggering on low-repetition rate signals that do not
provide a trigger before an auto baseline is generated.
SGL SWP (single sweep) trigger mode allows only one
sweep to be generated after being reset and is used to
obtain the waveform from a one-shot event.
ROLL and SCAN Storage modes are useful in captur
ing low-frequency and low-repetition rate waveforms. In
SCAN mode, receiving a trigger causes the pretrigger por
tion of the waveform to update as a block. The post
trigger waveform updates from the trigger point to the
right edge of the screen as new data is acquired. ROLL
Storage acquisitions differ from the Nonstore sweeps and
SCAN Storage mode in that a trigger signal is not used for
acquisition of the signal or displaying the waveform. The A
Sweep Logic circuitry provides gating and holdoff signals
used by the Storage circuitry to control its acquisition and
display cycles for all storage modes, except ROLL.
The A Gate signal applied to the A Miller Sweep Gen
erator circuit starts the Nonstore linear sweep with a ramp
time that is controlled by the A SEC/DIV switch setting.
3-3
Summary of Contents for 2230
Page 12: ...2230 Service X The 2230 Digital Storage Oscilloscope 4998 01 ...
Page 33: ...Operating Information 2230 Service Figure 2 5 Vertical controls and connectors 2 6 ...
Page 48: ...Operating Information 2230 Service Figure 2 11 X Y Plotter interfacing ...
Page 56: ...Theory of Operation 2230 Service 4999 01 3 2 Figure 3 1 Simplified block diagram ...
Page 68: ...Operating Information 2230 Service Figure 2 11 X Y Plotter interfacing ...
Page 76: ...Theory of Operation 2230 Service 4999 01 3 2 Figure 3 1 Simplified block diagram ...
Page 98: ...Theory of Operation 2230 Service 499 9 06 Figure 3 6 Horizontal Amplifier block diagram 3 24 ...
Page 111: ...Theory of Operation 2230 Service 3 37 Figure 3 9 Acquisition Memory timing ...
Page 190: ...Maintenance 2230 Service 999 14 Figure 6 3 Isolated kernel timing 6 9 ...
Page 329: ...PUT Figure 9 2 S em ico n d u cto r lea d co n fig u ratio n s ...
Page 332: ...2230Service CHASSIS MOUNTED PARTS ...
Page 334: ...A14 CH 1 LOGIC BOARD ...
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Page 347: ...i n 5 a O Q q o u S a o h UJ s a b c d e f g h j k l m n ...
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Page 355: ...WAVEFORMS FOR DIAGRAM 5 4999 83 ...
Page 358: ...I W L U O U rc a 4 2 s ...
Page 361: ...WAVEFORMS FOR DIAGRAM 6 S 84 ...
Page 362: ...2230 Service TEST SCOPE TRIGGERED ON U665 PIN 8 FOR WAVEFORMS 31 THROUGH 33 ...
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Page 366: ...A 1 6 S W E E P R EFEREN CE BOARD FIG 9 17 2230 Service Figure 9 17 A16 Sweep Reference board ...
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Page 371: ...Static Sensitive Devices See Maintenance Section CM I rv CD o 2230 Service ...
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Page 388: ...H K L M N 7 8 8 2 2 3 0 INPUT OUTFUT WIRING INTERCONNECT ...
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Page 394: ...2230 Service TEST SCOPE TRIGGERED ON U911 PIN 21 FOR WAVEFORMS 64 THROUGH 69 4999 92 ...
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Page 397: ...WAVEFORMS FOR DIAGRAM 15 TEST SCOPE TRIGGERED ON U9111 PIN 21 FOR WAVEFORMS 70 THROUGH 77 ...
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Page 423: ...W A V E F O R M SF O RD IA G R A M1 8 O c n ...
Page 424: ...Figure 9 22 A11A1 Input Output board ...
Page 430: ...Figure 9 23 A11A2 Vector Generator board ...
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Page 442: ...WAVEFORMS FOR DIAGRAM 22 4999 78 ...
Page 443: ...XY PLOTTER BOARD DIAGRAM 22 See Parts List for serial number ranges ...
Page 447: ...A21 RS 232 OPTION BOARD Flfi A 9 K 01 01 W M ...
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Page 459: ...A16 SWEEP REFERENCE ADJUSTMENT LOCATION ...
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