Tektronix 2230, Service Manual

Page: 109 / 483

Theory of Operation— 2230 Service
Before the start of an acquisition, U3105A pin 1 is held
LO by ACQENA. The LO keeps U3105A reset, putting a
LO on U3105A pin 5 and 1)3104C pin 9. The LO on the
input of NAND-gate U3104C causes the reset input of
U3105B (pin 13) to be HI. This allows the next delayed
SAVECLK to set U3105B. However before the start of an
acquisition, SAVECLK is held LO, U3105B remains reset,
the D input (pin 12) of U3105A is LO, and the WRITECLK
signal continues clocking a LO to an already LO output of
U3105A.
At the start of an acquisition, ACQENA goes HI on the
reset input of U3105A. On the first rising edge of the
delayed SAVECLK from U3101A pin 5, the fixed HI on the
D input of U3105B is clocked through to place a HI on the
D input of U3105A. On the next rising edge of WRITECLK,
that HI is passed to the Q output of U3105A and pin 9 of
NAND-gate U3104C. Assuming a HI is present on pin 10
of the NAND-gate, the output at pin 8 goes LO, resetting
U3105B, and on the next rising edge of WRITECLK the
LO from the Q output of,U3105B is clocked through
U3105A to end the ACQWRITE pulse. The ACQWRITE
pulse also removes the reset from U3105B so that the
next time it is clocked (by the next delayed SAVECLK), a
new ACQWRITE pulse is produced for the next Acquisition
Memory write.
The ACQWRITE signal goes to the Memory Control
multiplexer (U3417) to switch Acquisition Memory write
control to the acquisition system and is also applied to the
D input of flip-flop U3307A. One-half of a CONV clock
period later, the rising edge of CONV transfers the HI to
the DATAEN clock line at the Q output of the flip-flop.
DATAEN going HI enables NAND-gates U3313A and
U3313B in the Swap-Control circuitry to pass the SWAP
and SWAP register enabling signals. That and BUF-
FERCLK going HI transfers the data from the MIN/MAX
Registers onto the Acquisition Memory busses where it
can be written into memory.
If the SEC/DIV setting is such that SAVECLK is running
at 10 MHz, RNGA and RNGB will both be HI at the inputs
to NAND-gate U3104D. That makes the output of U3104A
also a HI. ENDREC goes LO only when an acquisition is
completed with a full record. The output of U3104B is
therefore LO, and U3104C is disabled, preventing a reset
from being passed to flip-flop U3105B. When ENDREC
does go LO, NAND-gate U3104C is enabled, and the reset
is passed to U3105B. On the next rising edge of
WRITECLK, ACQWRITE is clocked LO, switching memory
write control away from the acquisition system. When
operating at the fastest SAVECLK rates, a pair of Swap
Registers are enabled for the entire acquisition period to
immediately transfer data clocked in by BUFFERCLK to
the memory data buses.
CHANNEL SELECT. When only Channel 1 or Channel 2
is selected, the Microprocessor controls the choice via the
Acquisition Mode Register. For Channel 1 only, the
Microprocessor sets the CHI line LO, which sets U3102A
and holds the CHAN1 line LO. CHAN1 switches the
analog Channel Switch (U2101 on Diagram 16) to select
and apply the Channel 1 signal to the Sample-and-Hold
circuitry. Conversely, Channel 2 is selected when the
Microprocessor sets the CH2 line LO, which resets
U3102A and holds the CHAN1 line HI. When the signals
from both channels are to be added for ADD Mode, the
CHAN1 signal line is held LO, and the ADD signal is held
HI. This turns on both sides of the analog Channel Switch
to sum the input signals.
For dual-channel acquisitions, both the set and reset
input to flip-flop U3102A are HI, and channel switching is
controlled by ADCLK and the logic circuitry driving the D
input of the flip-flop. Channel switching is then determined
by the acquisition mode and the range setting of the
SEC/DIV switch. The channel switching is timed to place
the switching point between ADCLK positive transitions
(between sampling points) at the correct time for starting
waveform data into the acquisition system pipeline.
Multiplexer U4103 (Diagram 18) is switched by the
RNGA and RNGB signals from the Timebase Mode Regis­
ter. For SEC/DIV settings of 0.05 #ts to 1(Vs, CONV clock
and ADCLK run at 20 MHz and are in phase. In that case,
the SAVECLK signal phase is also correct for driving the
analog Channel Switch. For the remaining SEC/DIV switch
settings, the CONV clock runs at one-half the ADCLK
clock rate, and the control clocks developed by the delay
chain are delayed by 100 ns through each flip-flop rather
than by 50 ns as at the faster SEC/DIV settings. Since
this changes the delays of data going through the pipeline,
a delayed SAVECLK is required to switch channels at the
proper time. The 100 ns delayed SAVECLK from the Q
output of U4104B is delayed another 25 ns, by the rising
edge of ADCLK, before reaching the output of flip-flop
U3106A (Diagram 17).
Either the delayed SAVECLK from U3106A or
SAVECLK is selected by the multiplexer and applied to the
clock input of U3102B and to one input of NAND-gate
U3112 (pin 2). When Min-Max mode is selected, flip-flop
U3102B divides the selected clock by two. The channel is
switched only once for each SAVECLK so that the sam­
ples compared for min and max during a SAVECLK cycle
are all from the same channel.
When ACQENA on the reset input of U3102 is HI, the
flip-flop is enabled to toggle on each rising clock edge. If
Min-Max mode is also HI, NAND-gate U3313 is enabled to
pass the signal from the Q output of the flip-flop. NOR-
gate U3308, connected as an inverter, places a LO on
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