Tektronix 2230, Service Manual

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Maintenance— 2230 Service
and U4117) is loaded with OxFFI — 240 + 0x96 (0xF9F).
The Time Base Divisor Register (U4113) is set to 0x00,
the Acquisition Mode Register (U3310) is set to 0x85 and
the Time Base Mode Register (U4119) is set to 0x1 E. See
Table 6-12 for more acquisition data.
To start the acquisition a 0x10 is ORed into the Time
Base Mode Register (U4119), generating ACQENA TRUE
synchronous to CONV CLK. Two activities are then done
at the same time:
1. The microprocessor polls the Memory Address
Buffer bit 16 (U3428 pin 9) (ENDREC) 4000 times before
aborting the second activity.
2. The acquisition runs asynchronous to the micropro­
cessor.
CONV clock propagates through U4103B, U4125A, and
U4125B becoming SAVECLK. CONV and SAVECLK pro­
pagate through U4104B, U3101A, U3105B, U3105A
(becoming ACQWRITE), and U3417 to clock the data from
the swap (Acquisition Buffer Sequencer) registers (U3236
and U3239) into the Acquisition Memory (U3418 and
U3419) in 16-bit chunks. The signals from U3417 also
clock the acquisition Address Counters (U3423, U3424,
and U3425).
The microprocessor sets TEST FALSE (U3310) disa­
bling the DATA IN BUFFER (U3229). A LO TEST causes
the output of the DIAGNOSTIC CODE GENERATORS
(U3230 and U3231) to be used instead of the A/D CON­
VERTER data.
The microprocessor uses the ACQUISITION MODE
REGISTER (U3310) to tie MAXCLK and MINCLK (U3309
pin 7 and U3309 pin 9) to EVENCLK and ODDCLK
(U3101B pin 8 and U3103B pin 8) respectively through
U3309. ODDCLK and EVENCLK are 50% duty cycle com­
plements of each other and have a period of two CONV
clocks. This means that the MIN REGISTER is latched
with a test value and 50 ns later the MAX REGISTER is
latched with a value one greater. After another 25 ns the
swap (Acquisition Buffer/Sequencer) registers (U3236,
U3237, U3238, and U3239) latch a 16-bit word comprised
of the output of the MIN REGISTER and the MAX
REGISTER.
When the Acquisition Address Counter overflows PRE­
FULL (U3425 pin 7) goes HI. This in turn makes STO RDY
(U4226A pin 5) HI. CALTIMER (from U3310 pin 12) makes
multiplexer U4227 select STO RDY and pass it through to
U4227 pin
7.
Convert clock
(CONV) then
passes the signal
through U4228A, U4127C, and U4226B making TRIGD
(U4226B pin 9) HI. TRIGD enables the Post Record
Counter to count at RECCLK (CONV clock) rates.
One RECCLK after the Post Record Counter reaches a
hexadecimal count of FF0, U4105B creates ENDREC (not
end of record) LO. When the microprocessor finds
ENDREC LO, the values in the Acquisition Memory
Address Counters (U3423, U3424, and U3425) and the
Post Record Counter (U4115, U4116, and U4117) are
analyzed. Then the Acquisition Memory is checked to see
if it contains the proper values.
If an error is found, one of the following messages is
displayed on the crt:
HS_ACQ : latent END_OF_RECORD
HS_ACQ : acq_mem cntr < m em _ actu al> ' < >
< mem_expected >
HS_ACQ : prc <prc_actual> < > <prc_expected>
HS_ACQ : fill @ <fill_address> : <fill_actual> < >
<fill_expected>
Where:
Latent END_OF_RECORD means the microproces­
sor polled for an ENDREC 4000 times and never
saw one.
Acq_mem cntr means the completion value of the
Acquisition Memory Counter was not what was
expected (see Table 6-12).
Prc means the completion value of the Post Record
Counter was not what was expected
(see
Table 6-12).
Fill means the fill value at the indicated address was
not what was expected (see Table 6-12).
Prc_actual, prc_expected, mem_actual and
mem_expected are all 3 digit hexadecimal numbers.
Fill_address is a 4 digit hexadecimal number
representing an offset from 0x48000 (start of
Acquisition Memory).
Fill_actual and fill_expected are each 2 digit hexa­
decimal numbers.
TBD. This test checks the Time Base Divider string
using nine different Time Base Divider test ranges (rng).
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