Tektronix 2230, Service Manual

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Theory of Operation— 2230 Service
down by the Clock Generator to produce the various
clocking rates. The Time Base Mode Register latches con­
trol data bits from the Microprocessor data bus to set the
operating mode of the time base. These control bits switch
the Trigger Mux circuit to either A or B Trigger, enable the
trigger logic circuit, switch the clock multiplexer to change
the clocking rate, start a storage acquisition, and enable
interrupts to the Microprocessor. The programmable Time
Base Divider, under control of the Microprocessor via the
Time Base Divider Register, generates a sampling rate
that corresponds to the front-panel SEC/DIV switch
setting.
A Clock multiplexer at the end of the Time Base Divider
chain selects the output of the Time Base Divider, the
WRITECLK, the CONV clock, or an external clock signal
to generate the SAVECLK signal.
The Digital Time Base Trigger Logic circuit looks at
whether the pretrigger data portion of the record has been
filled. If the pretrigger portion is full, then the A or B Gate
generates the trigger. When a trigger is generated in
Repetitive Storage mode, the Clock Delay Timer measures
the time delay between the arrival of the trigger and the
convert clock. The time difference value is used by the
Microprocessor to accurately position the acquired data
with respect to the actual trigger point.
The delay difference between the start of the acquisi­
tion and the occurrence of the B trigger is also measured.
This value is only used in BOTH HORIZONTAL MODE
when running the B Horizontal display in Triggerable After
Delay to provide a readout of the time delay between the
A Trigger and the B Trigger points.
Acquisitions are counted to determine when a full
record of data has been stored (ENDREC) and to keep
track of the beginning and ending memory locations of the
record. The Record Counter is also programmable to pro­
vide for the different record lengths for one-channel or
two-channel acquisitions, different Pretrigger selections,
and either 4K-byte or IK-byte record length.
Digital Display
A custom 1C handles the digital display generation. The
Display Controller functions as an interface between the
processor bus, display memory (RAM), and vector genera­
tors to form waveform and character displays on the crt.
The controller reads a display list from the Display
Memory and drives X- and Y-Vector Generators to create
the waveform and readout displays. Z-Axis control signals
are also generated to drive the crt Z-Axis Amplifier for
Stored waveform and Readout intensity control. Control
signals to the Microprocessor and Display Memory are
generated in response to a processor read/write request.
Digital-to-analog converters take the digital data bytes
supplied from the Display Memory via the Display Con­
troller and change them to the X- and Y-Axis analog
signals that drive the Horizontal and Vertical Vector Gen­
erators. The vector signals are applied to the Horizontal
and Vertical Output Amplifiers to produce the STORE
mode deflection signals and NON STORE mode character
readout.
The Display Memory is six 16-K X 4-bit dynamic ran­
dom access memories (RAM). Four of the RAMs provide
the 8-bit data bytes of the stored waveform, and the
remaining RAMs store each data-byte's intensity and
Status attributes. A 4-bit word in each RAM is selected by
latching a row address followed by a column address.
Data is either stored or read out (as the operation in pro­
gress requires).
Vector Generator
X- and Y-Axis analog signals from the Digital Display
are converted by the Vector Generators into the vector
signals used to drive the crt deflection plates. Vector
signals are produced for the stored waveforms, the menu
displays, and the readouts. The Vector Generator is
switched to the dot-display mode for equivalent-time sam­
pling waveforms and X-Y displays.
The X-Y Plotter driver circuit is included in this portion
of the circuitry. When the X-Y Plotter is enabled, x-axis
and y-axis signals are switched via the plot multiplexer to
the x-axis and y-axis plot amplifiers. The VECT SMPL sig­
nal is switched via the same multiplexer to drive the Pen-
Down amplifier.
Z-Axis
The Z-Axis Amplifier has input signals from multiple
sources that control the crt intensity on a time-shared
basis. Nonstore intensity signals are the level inputs from
the A and B INTENSITY controls that are controlled by the
Alternate Display switching and B Z-Axis Logic circuits.
Additional Z-Axis drive current is supplied during the
intensified portion of an A trace during the B Sweep when
BOTH Horizontal display mode is selected. The remaining
nonstore signals that have control of the display bright­
ness are the EXT Z-AXIS INPUT signal, the CHOP mode
blanking signal, and the XY control signal. All of these
sources are added to provide the time-shared nonstore
displays.
For the Store waveform and the Menu and Readout
character displays, an additional Z-Axis drive signal from
the STORAGE/READOUT INTENSITY control is switched
on and off by the Display Controller. The controller signals
determine when the stored waveforms and the readout
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