Tektronix 2230, Service Manual

Page: 84 / 483

Theory of Operation— 2230 Service
reversed, reversing the polarity of the output signal to pro­
duce an inverted Channel 2 trace and Channel 2 storage
acquisition signal. The inverted/noninverted state is read
by the Microprocessor, and an indicator is displayed in the
crt readout adjacent to the CH 2 VOLTS/DIV readout to
indicate to the user when INVERT is in effect. Invert Bal
potentiometer R75 is adjusted for minimal dc trace shift
when the INVERT button is changed between IN and
OUT.
VERTICAL PREAMPLIFIERS
The Channel 1 and Channel 2 Vertical Preamplifiers,
shown on Diagram 2, are identical in operation. Operation
of the Channel 1 amplifier is described. Differential signal
current from the Paraphase Amplifier is amplified to pro­
duce drive current to the Delay Line Driver and supply the
Channel 1 signal to the Storage Acquisition circuitry. Inter­
nal trigger signals for the Trigger circuitry are picked off
prior to the Vertical Preamplifier. The Channel Switch cir­
cuitry controls channel selectibn for the Nonstore crt
display. STORE mode signal acquisition and display, and
the selection of either STORE or NON STORE, is con­
trolled by the Display Controller circuitry.
Common-base transistors Q102 and Q103, which com­
plete the Paraphase Amplifier portion of the circuitry
shown on Diagram 1, convert differential current from the
Paraphase Amplifier into level-shifted voltages that drive
the bases of the input transistors of Vertical Preamplifier
U130. Differential internal trigger signals are picked off at
this point from the collector signals of Q1C2 and Q103
before Vertical POSITION dc offset is added to the input
signals.
The collector current of each input transistor of U130 is
the emitter current for two of the differential output
transistors. One of the collectors of each output pair sup­
plies one side of the differential Nonstore signal to the
Delay Line Driver, and the other collector in each pair sup­
plies one side of the differential Channel signal to the
Storage Acquisition circuitry. The base bias voltages of the
output transistors are controlled by the Channel Switch
Logic circuitry. The switching circuitry determines which
channel is active (CH 1, CH 2 or both for ADD) in NON
STORE, and which channel supplies the Storage Acquisi­
tion signal in STORE.
Vertical POSITION control R112 adds an offset voltage
to the pair of differential transistors, Q114 and Q115, that
supply the emitter current to the Preamplifier input transis­
tors. Unequal collector currents from Q114 and Q115 go
to the input transistors to introduce the vertical position
offset to the Channel 1 NON STORE signal. Output
signals from Q114 and Q115 are applied to a Storage
Vertical Position conditioning circuit where dc offset adjust­
ments provide tracking corrections between the vertical
positions of the NON STORE and the STORE signals.
When Channel 1 is selected to drive the Delay Line
Driver, the Q output (pin 5) of U540A is HI. That HI is
switched through U7201 to the bases of the nonstore sig­
nal transistors (connected to pin 14 of U130). These
transistors are then forward-biased, and the Channel 1
signal is conducted to the Channel Switch circuit. If Chan­
nel 1 is not selected, then the Q output of U540A is LO,
and the nonstore signal transistors are reverse-biased to
prevent the Channel 1 nonstore signal from being
displayed. The gain of the Preamplifier is set by adjusting
R145 to control the signal current that is shunted between
the two differential outputs. Amplifier gain is reduced by
the current shunted between the two halves of the
Preamplifier.
Channel Switch Logic
The Channel Switch Logic circuitry, shown on
Diagram 2, utilizes the front-panel VERTICAL MODE and
STORE/NON STORE mode switches to select the crt
display format. See Figure 3-3 for a block diagram of the
circuit.
When any display mode other than X-Y is selected, the
XY line connected to S550 is at ground potential. VERTI­
CAL MODE switches S545 and S550 control the connec­
tion between the XY control line and the Set and Reset
inputs of flip-flop U540A for the nonstore display formats.
CHANNEL 1 DISPLAY ONLY. The CH 1 position of
S550 grounds the Set input (pin 4) of U540A while the
Reset input (pin 1) is held HI by pull-up resistor R539. This
produces a HI and a LO on the Q and (Toutputs of U540A
respectively. The levels are selected by multiplexer U7201,
biasing on the Channel 1 nonstore output transistors in
U130, allowing the Channel 1 input signal to drive the
Delay Line Driver. The Channel 2 Preamplifier nonstore
output transistors in U180 are biased off.
CHANNEL 2 DISPLAY ONLY. The CH 2 position of
S550 holds the Reset input of U540A LO through CR538,
and the Set input is held HI by pull-up resistor R538. The
outputs of U540A are then Q LO and HI biasing on the
Channel 2 Preamplifier nonstore output transistors (in
U180) and biasing off the Channel 1 Preamplifier nonstore
output transistors (in U130). Channel 2 then supplies the
signal to drive the Delay Line Driver.
To display the ADD, ALT, or CHOP formats, S550 must
be in the BOTH position to ground the A, C, and F pins of
S545.
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