Tektronix 2230, Service Manual

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Theory of Operation— 2230 Service
Switch position pickoffs supply the SEC/DIV switch setting
information to the Microprocessor for use in STORE mode
horizontal timing. The A SEC/DIV switch setting is also
displayed on the crt for both Store and Nonstore
operation.
B Sweep
The Alternate B Sweep Circuitry controls the Nonstore
BOTH and B Delayed Horizontal mode displays. This cir­
cuitry includes the B Miller Sweep Generator and B Sweep
Logic circuitry. STORE mode B timing is controlled by the
B SEC/DIV switch. BOTH Horizontal mode is not available
with STORE. In STORE mode, the BOTH selection
displays an A Intensified Trace only. The intensified zone
on the A trace indicates the position and approximate
amount of the A trace that is displayed by the B Delayed
Display.
Horizontal
Nonstore A and B Sweep signals (or the X-Axis signal
from the X-Y Amplifier in the nonstore X-Y Display mode)
are applied to the Horizontal Preamplifier where one is
selected and amplified. Gain in the Preamplifier is switch-
able between XI and X I0. The X I0 gain is used for Non­
store X I0 Magnification. STORE mode X I0 expansion is
done digitally and reflected in the horizontal deflection sig­
nals supplied after the Horizontal Preamplifier. Horizontal
positioning of both the Store and the nonstore display is
done by applying a horizontal position dc offset to the Hor­
izontal Preamplifier. The amplified nonstore horizontal sig­
nal is applied to the Horizontal Mux circuit where it is
available for selection.
STORE mode horizontal deflection signals are also
applied to the Horizontal Mux. Selection of either the non­
store sweep signals or the store deflection signals is done
by control signals from the Channel Switch Logic in the
Vertical circuitry. The selected horizontal deflection signals
are then amplified by the Horizontal Output Amplifier to
the levels needed to drive the crt’s horizontal deflection
plates.
Microprocessor
The Microprocessor (MPU) controls the digital storage
and display sections of the oscilloscope. Under firmware
control (firmware is the programmed instructions contained
in read-only memory), the Microprocessor monitors the
operation of the instrument and sets up the circuitry to
perform as dictated by the front-panel control settings.
Data transfer to and from the Microprocessor and address
selection of a device to be communicated with are done
over a 20-line I/O bus. The lower eight lines (ADO through
AD7) form a combined address/data bus while the remain­
ing 12 lines (A8 through A19) are for addressing only. Tim­
ing for the execution of instructions, addressing, and data
transfers is provided by an external, crystal-controlled
oscillator that drives the Microprocessor clock generator.
The Microprocessor clock circuit further divides the input
clock frequency to generate two lower clock frequencies.
The clock circuit also generates the Ready and Reset con­
trol signals to the Microprocessor.
Storage front-panel control settings
are
passed to the
Microprocessor via eight-bit bus drivers. Settings of the
analog front-panel controls and switches are also provided
to the MPU, but via different bus drivers. The Status ADC
and Bus Interface circuitry provides the interfaces from the
analog front-panel controls to the data bus.
Status ADC and Bus Interface
Switch settings and status bits are applied directly to
bus drivers. Each data bit then corresponds to a switch
setting (either open or closed) or a status bit logic level
(either HI or LO). Analog front-panel information is multi­
plexed to an analog-to-digital converter where it is con­
verted to a digital value and applied to a bus driver. When
the Microprocessor reads the bus, it obtains a data byte
that represents the position value for a single control
rather than the switch or status data bits of the digital-
type information. The Microprocessor determines the con­
trol settings from the value of the data bytes or status bits
received and sets up the digital storage circuits
accordingly.
Storage Acquisition
Input signals to be digitized are selected by the Channel
Switch. Either or both (for ADD) of the input signals picked
off from the Vertical Preamplifier may be selected. The
differential output signal
from
the Channel Switch is con­
verted to a single-ended signal for application to the
Sample-and-Hold amplifier. The input diode bridge in the
Sample-and-Hold circuit is strobed to pass a sample of the
signal to charge the hold capacitor. While the signal sam­
ple is held for conversion, the diode bridge is reverse
biased, and the charge on the Hold capacitor remains at a
fixed level. The sample buffer amplifier applies the voltage
level on the Hold capacitor to the Analog-to-Digital Con­
verter stage for conversion to an eight-bit digital signal.
The output signals are then shifted from the emitter-
coupled logic (ECL) level obtained from the ADC to the
transistor-transistor-logic level (TTL) and passed to the
digitized signal bus for transfer to the Acquisition Memory.
Digital Acquisition
Digitized waveforms are transferred from the ECL-to-
TTL level shifters via the digitized data bus to the A/D
Buffer of the Acquisition Memory circuit. The buffered data
is applied to two identical registers; the Min Register and
the Max Register. Data is alternately clocked into the
registers by the MINCLK and MAXCLK clock signals. The
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