Supero SUPER P6DGH, User Manual

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BIOS User's Manual
5-8
- The GX asserts SERR# for one clock when it detects a target abort during a GX-initiated PCI cycle .
- The GX can also assert SERR# when a PCI parity error occurs during the address or data phase.
- The GX can assert SERR# when it detects a PCI address or data parity error on the AGP.
- The GX can assert SERR# upon the detection of access to an invalid entry in the Graphics Aperture
Translation Table.
- The GX can assert SERR# upon detecting an invalid AGP master access outside of the AGP aperture and
outside of the main DRAM range (i.e. in the 640k -1M range or above TOM).
- The GX can assert SERR# upon detecting an invalid AGP master access outside of the AGP aperture.
- The GX asserts SERR# for one clock when it detects a target abort during a GX-initiated AGP cycle.
PERR#
This option is to signal the occurrence of data parity errors on the PCI
bus. The settings are Enabled or Disabled. Set to Enabled to enable
the PERR# signal.
WSC# Handshake (Write Snoop Complete)
This signal is asserted active to indicate that all the snoop activity on the
CPU bus on behalf of the last PCI-DRAM write transaction is complete and
that it is safe to send the APIC interrupt message. The settings for this
option are Enabled or Disabled. Set to Enabled to enable handshaking
for the WSC# signal.
USWC Write Post
The settings for this option are Enabled or Disabled. This option sets
the status of USWC (Uncacheable, Speculative or Write-Combining)
posted writes and is used to combine several partial writes to the frame
buffer into a single write to reduce the data bus traffic. Set to Enabled
to enable USWC posted writes to I/O. Set to Disabled to disable USWC
posted writes to I/O.
BX/GX Master Latency Timer (CLKs)
This option specifies the master latency timings (in PCI clocks) for
devices in the computer. It defines the number of PCI clocks a PCI master
can own on the bus after the PCI central arbiter removes the grant signal.
The settings are Disabled, 32, 64, 96, 128, 160, 192 or 224.
Multi-Trans Timer (CLKs)
This option specifies the multi-trans latency timings (in PCI clocks) for
devices in the computer. It is used to reduce overhead switching
between different masters. The settings are Disabled, 32, 64, 96, 128,
160, 192 or 224.