Sun Microsystems Sun Blade 100, Service Manual

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C-14 Sun Blade 100 Service Manual • October 2000
C.5.2.3 Power-On LED Control
The M1535D provides an LED output which is software controllable to turn on or
turn off the LED or to have LED blink at the rate of 1Hz or 2Hz.
C.5.3 Optional Secondary Hard Drive
The Sun Blade 100 has a provision for a second hard drive on the hard drive tray.
FIGURE C-5
shows the configuration.
FIGURE C-5
Secondary Hard Drive Cabling Configuration
C.6 Memory Architecture
The Sun Blade 100 system uses a 168-pin, JEDEC standard, dual-in-line, 3.3V,
unbuffered, synchronous DRAM module. The Memory Control Unit (MCU) is
embedded within the CPU. All address, control signals and clocks are driven off of
the processor and directly drive the memory sub-system on the motherboard.
The CPU L2 cache megacell reserves a 2 Gbyte region for cacheable main memory.
The memory controller only supports 2 Gbytes of space. The system has four DIMM
slots on the motherboard. Because the memory data bus width is equal to the
DIMMs (64-bit data, plus 8-bit ECC) they can be installed one at a time and with
mixed sizes. The interface between processor and memory sub-system on the
motherboard consists of:
■
Two sets of multiplexed row-column address bank select address.
■
Two sets of bank address
■
Four RAS
■
Four CAS
■
Four WE
■
Eight clocks
■
Eight CS
FIGURE C-6
describes the system memory interface.
Riser board (J503)
Optional second hard drive
(Secondary HDD)
IDE 2