Sun Microsystems Sun Blade 100, Service Manual

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C-18 Sun Blade 100 Service Manual • October 2000
C.7 Address Mapping
This section provides the overview of address partitioning and software-visible
registers and their respective functionality. The physical address associated with
each of these registers is listed, along with a brief description of the register. For
further details on the description and functionality of the registers and chips, refer to
the respective chip specification.
■
Section C.7.1 “Port Allocations” on page C-18
■
Section C.7.2 “PCI Address Assignments” on page C-19
C.7.1 Port Allocations
The following table lists the system port allocations. The CPU divides the physical
address space among:
■
Main memory (DRAM)
■
PCI (which is further subdivided into the primary PCI bus (PCI-A) and the
secondary PCI bus (PCI-B bus) when the APB ASIC is used).
TABLE C-8
Port Allocations
Address Range in
PA<40:0>
Size Port Access Access Type
0x000.0000.0000 -
0x000.3FFF.FFFF 1 Gbyte Main memory Cacheable
0x000.4000.0000 -
0x1FF.FFFF.FFFF Do not use Undefined Cacheable
0x1FC.0000.0000 -
0x1FD.FFFF.FFFF 8 Gbytes UPA graphics Non-cacheable
0x1FE.0000.0000 -
0x1FF.FFFF.FFFF 8 Gbytes CPU IO Non-cacheable