Sun Microsystems Sun Blade 100, Service Manual

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C-20 Sun Blade 100 Service Manual • October 2000
Boot PROM
The PCIO ASIC is strapped so that the red mode trap address is:
■
UPA: 0x1FF.F000.0000
■
PCI: 0xF000.0000
■
EBus2: 0x00.0000
The following table lists the boot and flash PROM address assignments.
C.8 Interrupts
C.8.1 Interrupt Interface
The CPU uses a 6-bit encoded interrupt vector mechanism. An IChip2 is used as an
interrupt concentrator, which will receive all the system interrupts and encode the
interrupts into a 6-bit interrupt vector. The interrupt vector is then registered and
synchronized externally with PCI clock before sending to the processor. The
difference between the IChip and IChip2 is the package: IChip is a 120p-pin MQFP
and IChip2 is a 128-pin TQFP.
C.9 Power
The Sun Blade 100 is Energy Star compliant. The Sun Blade 100 uses the Tier2,
Guideline B of EPA’s 3.0 MOU. This means that when Sun Blade 100 is in a Power
Managed state the maximum power consumption will be 24 Watts or less.
In order to achieve the goal, power-saving techniques need to be implemented on
the most power hungry devices in a computer system such as CPU, memory
subsystem and peripheral devices. When put into Energy Star mode, the
UltraSPARC-IIe processor will reduce the core clock speed by dividing the input
clock by a factor of six internally. The PCI clocks to the PCI slots will be stopped.
TABLE C-10
Boot PROM/Flash PROM Address Assignments
Offset Register Description Type Size
0x00.0000 - 0xFF.FFFF Flash PROM/EPROM R 1 or 4 bytes